default search action
Behzad Razavi
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [c81]Kshitiz Tyagi, Behzad Razavi:
A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm2. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j91]Yu Zhao
, Onur Memioglu, Long Kong
A 56-GHz Fractional-N PLL With 110-fs Jitter. IEEE J. Solid State Circuits 58(1): 57-67 (2023) - [j90]Yu Zhao
A 20-GHz PLL With 20.9-fs Random Jitter. IEEE J. Solid State Circuits 58(6): 1597-1609 (2023) - [j89]Hossein Razavi
A Study of Injection Locking in Oscillators and Frequency Dividers. IEEE J. Solid State Circuits 58(8): 2129-2140 (2023) - [j88]Onur Memioglu
A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation. IEEE J. Solid State Circuits 58(8): 2141-2156 (2023) - [j87]Kshitiz Tyagi
Performance Bounds of ADC-Based Receivers Due to Clock Jitter. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1749-1753 (2023) - [c80]Matias Jara, Behzad Razavi:
A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply. CICC 2023: 1-2 - [c79]Pawan K. Khanna, Yu Zhao, Mahdi Forghani, Behzad Razavi:
A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis. ESSCIRC 2023: 501-504 - [c78]Mahdi Forghani, Yu Zhao, Pawan K. Khanna, Behzad Razavi:
A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j86]Atharav Atharav
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS. IEEE J. Solid State Circuits 57(1): 54-67 (2022) - [j85]Hossein Razavi
A 0.4-6 GHz Receiver for Cellular and WiFi Applications. IEEE J. Solid State Circuits 57(9): 2640-2657 (2022) - [j84]Guanrong Hou
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance. IEEE J. Solid State Circuits 57(9): 2856-2867 (2022) - [j83]Seyed Mehrdad Babamir
Relation Between INL and ACPR of RF DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3877-3887 (2022) - [c77]Mahdi Forghani, Behzad Razavi:
Circuit Bandwidth Requirements for NRZ and PAM4 Signals. ISCAS 2022: 990-994 - [c76]Yu Zhao, Behzad Razavi:
Phase Noise Integration Limits for Jitter Calculation. ISCAS 2022: 1005-1008 - [c75]Makar Chand Snai, Behzad Razavi:
Optimal Distribution of High-Speed Clocks on Transceiver Chips. ISCAS 2022: 1038-1042 - [c74]Onur Memioglu, Yu Zhao, Behzad Razavi:
A 300GHz 52mW CMOS Receiver with On-Chip LO Generation. ISSCC 2022: 1-3 - [c73]Yu Zhao, Onur Memioglu, Behzad Razavi:
A 56GHz 23mW Fractional-N PLL with 110fs Jitter. ISSCC 2022: 1-3 - 2021
- [j82]Behzad Razavi
Jitter-Power Trade-Offs in PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1381-1387 (2021) - [c72]Behzad Razavi:
Low-Power Techniques for Wireline Systems. ESSCIRC 2021: 515-522 - [c71]Atharav Atharav, Behzad Razavi:
11.7 A 56Gb/s 50mW NRZ Receiver in 28nm CMOS. ISSCC 2021: 192-194 - [c70]Guanrong Hou, Behzad Razavi:
A 56-Gb/s 8-mW PAM4 CDR/DMUX with High Jitter Tolerance. VLSI Circuits 2021: 1-2 - [c69]Hossein Razavi, Behzad Razavi:
A 0.4-6 GHz Receiver for LTE and WiFi. VLSI Circuits 2021: 1-2 - [c68]Hossein Razavi, Behzad Razavi:
A 27-73 GHz Injection-Locked Frequency Divider. VLSI Circuits 2021: 1-2 - [c67]Yu Zhao, Behzad Razavi:
A 19-GHz PLL with 20.3-fs Jitter. VLSI Circuits 2021: 1-2 - 2020
- [j81]Seyed Mehrdad Babamir
A Digital RF Transmitter With Background Nonlinearity Correction. IEEE J. Solid State Circuits 55(6): 1502-1515 (2020) - [c66]Behzad Razavi:
Lower Bounds on Power Consumption of Clock Generators for ADCs. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j80]Long Kong
An Inductorless 20-Gb/s CDR With High Jitter Tolerance. IEEE J. Solid State Circuits 54(10): 2857-2866 (2019) - [j79]Xavier Bosch-Lluis
Instrument Design and Performance of the High-Frequency Airborne Microwave and Millimeter-Wave Radiometer. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 12(11): 4563-4577 (2019) - [c65]Fei Song, Yu Zhao, Bart Wu, Litian Tang, Leon Lin, Behzad Razavi:
A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax. ISSCC 2019: 264-266 - 2018
- [j78]Long Kong
A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25fREF. IEEE J. Solid State Circuits 53(6): 1707-1718 (2018) - [j77]Yikun Chang
An 80-Gb/s 44-mW Wireline PAM4 Transmitter. IEEE J. Solid State Circuits 53(8): 2214-2226 (2018) - [c64]Yikun Chang, Abishek Manian, Long Kong, Behzad Razavi:
A 32-mW 40-Gb/s CMOS NRZ transmitter. CICC 2018: 1-4 - [c63]Behzad Razavi:
An Alternative Analysis of Noise Folding in Fractional-N Synthesizers. ISCAS 2018: 1-4 - [c62]Long Kong, Yikun Chang, Behzad Razavi:
A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance. VLSI Circuits 2018: 271-272 - 2017
- [j76]Long Kong
A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer. IEEE J. Solid State Circuits 52(8): 2117-2127 (2017) - [j75]Abishek Manian
A 40-Gb/s 14-mW CMOS Wireline Receiver. IEEE J. Solid State Circuits 52(9): 2407-2421 (2017) - [j74]John R. Long, Jan Craninckx
Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. IEEE J. Solid State Circuits 52(10): 2519-2520 (2017) - [j73]Joung Won Park, Behzad Razavi:
Analysis of Second-Order Intermodulation in Miller Bandpass Filters. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 264-268 (2017) - [c61]Long Kong, Behzad Razavi:
19.5 A 2.4GHz RF fractional-N synthesizer with 0.25fREF BW. ISSCC 2017: 330-331 - 2016
- [j72]Long Kong, Behzad Razavi:
A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer. IEEE J. Solid State Circuits 51(3): 626-635 (2016) - [j71]Aliakbar Homayoun
On the Stability of Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 741-750 (2016) - [c60]Abishek Manian, Behzad Razavi:
23.8 A 40Gb/s 14mW CMOS wireline receiver. ISSCC 2016: 412-414 - [c59]Long Kong, Behzad Razavi:
A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizer. VLSI Circuits 2016: 1-2 - 2015
- [j70]Jun Won Jung, Behzad Razavi:
A 25 Gb/s 5.8 mW CMOS Equalizer. IEEE J. Solid State Circuits 50(2): 515-526 (2015) - [j69]Aliakbar Homayoun, Behzad Razavi:
A Low-Power CMOS Receiver for 5 GHz WLAN. IEEE J. Solid State Circuits 50(3): 630-643 (2015) - [j68]Sy-Chyuan Hwu, Behzad Razavi:
An RF Receiver for Intra-Band Carrier Aggregation. IEEE J. Solid State Circuits 50(4): 946-961 (2015) - [c58]Behzad Razavi:
The future of radios. ISCAS 2015: 1-8 - [c57]Long Kong, Behzad Razavi:
25.7 A 2.4GHz 4mW inductorless RF synthesizer. ISSCC 2015: 1-3 - [c56]Joseph Palackal Mathew, Long Kong, Behzad Razavi:
A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply. VLSIC 2015: 66- - [c55]Abishek Manian, Behzad Razavi:
A 40-Gb/s 9.2-mW CMOS equalizer. VLSIC 2015: 226- - 2014
- [j67]Aliakbar Homayoun, Behzad Razavi:
Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise. IEEE J. Solid State Circuits 49(2): 384-391 (2014) - [j66]Shiuh-Hua Wood Chiang, Hyuk Sun, Behzad Razavi:
A 10-Bit 800-MHz 19-mW CMOS ADC. IEEE J. Solid State Circuits 49(4): 935-949 (2014) - [j65]Sedigheh Hashemi, Behzad Razavi:
Analysis of Metastability in Pipelined ADCs. IEEE J. Solid State Circuits 49(5): 1198-1209 (2014) - [j64]Sedigheh Hashemi, Behzad Razavi:
A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate. IEEE J. Solid State Circuits 49(8): 1739-1750 (2014) - [j63]Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8 Bit 4 GS/s 120 mW CMOS ADC. IEEE J. Solid State Circuits 49(8): 1751-1761 (2014) - [j62]Joung Won Park, Behzad Razavi:
Channel Selection at RF Using Miller Bandpass Filters. IEEE J. Solid State Circuits 49(12): 3063-3078 (2014) - [c54]Abishek Manian, Behzad Razavi:
A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply. CICC 2014: 1-4 - [c53]Behzad Razavi:
Recent developments in RF receivers. CICC 2014: 1-78 - [c52]Behzad Razavi:
The role of translational circuits in RF receiver design. CICC 2014: 1-8 - [c51]Jun Won Jung, Behzad Razavi:
2.4 A 25Gb/s 5.8mW CMOS equalizer. ISSCC 2014: 44-45 - [c50]Joung Won Park, Behzad Razavi:
20.8 A 20mW GSM/WCDMA receiver with RF channel selection. ISSCC 2014: 356-357 - [c49]Sy-Chyuan Hwu, Behzad Razavi:
A receiver architecture for intra-band carrier aggregation. VLSIC 2014: 1-2 - 2013
- [j61]Jun Won Jung, Behzad Razavi:
A 25-Gb/s 5-mW CMOS CDR/Deserializer. IEEE J. Solid State Circuits 48(3): 684-697 (2013) - [j60]Joung Won Park, Behzad Razavi:
A Harmonic-Rejecting CMOS LNA for Broadband Radios. IEEE J. Solid State Circuits 48(4): 1072-1084 (2013) - [j59]Bibhudatta Sahoo, Behzad Razavi:
A 10-b 1-GHz 33-mW CMOS ADC. IEEE J. Solid State Circuits 48(6): 1442-1452 (2013) - [j58]Behzad Razavi:
Design Considerations for Interleaved ADCs. IEEE J. Solid State Circuits 48(8): 1806-1817 (2013) - [j57]Aliakbar Homayoun, Behzad Razavi:
Analysis of Phase Noise in Phase/Frequency Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 529-539 (2013) - [c48]Sedigheh Hashemi, Behzad Razavi:
A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate. CICC 2013: 1-4 - [c47]Aliakbar Homayoun, Behzad Razavi:
A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications. CICC 2013: 1-4 - [c46]Behzad Razavi:
Charge steering: A low-power design paradigm. CICC 2013: 1-8 - [c45]Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8-Bit 4-GS/s 120-mW CMOS ADC. CICC 2013: 1-4 - 2012
- [c44]Sedigheh Hashemi, Behzad Razavi:
A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion. CICC 2012: 1-4 - [c43]Behzad Razavi:
Problem of timing mismatch in interleaved ADCs. CICC 2012: 1-8 - [c42]Bibhudatta Sahoo, Behzad Razavi:
A 10-bit 1-GHz 33-mW CMOS ADC. VLSIC 2012: 30-31 - [c41]Joung Won Park, Behzad Razavi:
A harmonic-rejecting CMOS LNA for broadband radios. VLSIC 2012: 80-81 - [c40]Jun Won Jung, Behzad Razavi:
A 25-Gb/s 5-mWCMOS CDR/deserializer. VLSIC 2012: 138-139 - 2011
- [j56]Behzad Razavi:
A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology. IEEE J. Solid State Circuits 46(4): 894-903 (2011) - [j55]Sameh A. Ibrahim
Low-Power CMOS Equalizer Design for 20-Gb/s Systems. IEEE J. Solid State Circuits 46(6): 1321-1336 (2011) - [j54]ChuanKang Liang, Behzad Razavi:
Transmitter Linearization by Beamforming. IEEE J. Solid State Circuits 46(9): 1956-1969 (2011) - [c39]John R. Long, Hooman Darabi, Frank Op't Eynde, Behzad Razavi, Robert Bogdan Staszewski
Cellular and wireless LAN transceivers: From systems to circuit design. ISSCC 2011: 524 - 2010
- [j53]Behzad Razavi:
Cognitive Radio Design Challenges and Techniques. IEEE J. Solid State Circuits 45(8): 1542-1553 (2010) - [j52]Mohamed Aboudina, Behzad Razavi:
A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 966-970 (2010) - [c38]Sameh A. Ibrahim
A 20Gb/s 40mW equalizer in 90nm CMOS technology. ISSCC 2010: 170-171 - [c37]Ian Galton, Behzad Razavi, John Cowles, Peter R. Kinget
CMOS phase-locked loops for frequency synthesis. ISSCC 2010: 521
2000 – 2009
- 2009
- [j51]ChuanKang Liang, Behzad Razavi:
Systematic Transistor and Inductor Modeling for Millimeter-Wave Design. IEEE J. Solid State Circuits 44(2): 450-457 (2009) - [j50]Ali Parsa, Behzad Razavi:
A New Transceiver Architecture for the 60-GHz Band. IEEE J. Solid State Circuits 44(3): 751-762 (2009) - [j49]Bibhudatta Sahoo, Behzad Razavi:
A 12-Bit 200-MHz CMOS ADC. IEEE J. Solid State Circuits 44(9): 2366-2380 (2009) - [j48]Ashutosh Verma, Behzad Razavi:
A 10-Bit 500-MS/s 55-mW CMOS ADC. IEEE J. Solid State Circuits 44(11): 3039-3050 (2009) - [j47]Behzad Razavi:
Design of Millimeter-Wave CMOS Radios: A Tutorial. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 4-16 (2009) - [j46]Behzad Razavi:
The Role of PLLs in Future Wireline Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1786-1793 (2009) - [c36]Behzad Razavi:
Challenges in the design of cognitive radios1. CICC 2009: 391-398 - [c35]Ashutosh Verma, Behzad Razavi:
A 10b 500MHz 55mW CMOS ADC. ISSCC 2009: 84-85 - [c34]Bibhudatta Sahoo, Behzad Razavi:
U-PAS: A user-friendly ADC simulator for courses on analog design. MSE 2009: 77-80 - 2008
- [j45]Behzad Razavi:
A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider. IEEE J. Solid State Circuits 43(2): 477-485 (2008) - [j44]Behzad Razavi:
A Millimeter-Wave Circuit Technique. IEEE J. Solid State Circuits 43(9): 2090-2098 (2008) - [c33]Behzad Razavi:
Phase-locking in wireline systems: Present and future. CICC 2008: 615-622 - [c32]Ali Parsa, Behzad Razavi:
A 60GHz CMOS Receiver Using a 30GHz LO. ISSCC 2008: 190-191 - 2007
- [j43]Hamid Rafati, Behzad Razavi:
A Receiver Architecture for Dual-Antenna Systems. IEEE J. Solid State Circuits 42(6): 1291-1299 (2007) - [j42]Srikanth Gondi, Behzad Razavi:
Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers. IEEE J. Solid State Circuits 42(9): 1999-2011 (2007) - [j41]Behzad Razavi:
Heterodyne Phase Locking: A Technique for High-Speed Frequency Division. IEEE J. Solid State Circuits 42(12): 2887-2892 (2007) - [c31]Behzad Razavi:
Design Considerations for Future RF Circuits. ISCAS 2007: 741-744 - [c30]Behzad Razavi:
CMOS Transceivers at 60 GHz and Beyond1. ISCAS 2007: 1983-1986 - [c29]Behzad Razavi:
A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider. ISSCC 2007: 188-596 - [c28]Behzad Razavi:
Heterodyne Phase Locking: A Technique for High-Frequency Division. ISSCC 2007: 428-429 - [c27]Cheng-Chung Hsu, Fong-Ching Huang, Chih-Yung Shih, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Behzad Razavi:
An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration. ISSCC 2007: 464-615 - 2006
- [j40]Behzad Razavi:
A 60-GHz CMOS receiver front-end. IEEE J. Solid State Circuits 41(1): 17-22 (2006) - [c26]Khaled Abdelfattah, Behzad Razavi:
Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators. CICC 2006: 197-200 - [c25]Ashutosh Verma, Behzad Razavi:
Frequency-Based Measurement of Mismatches Between Small Capacitors. CICC 2006: 481-484 - [c24]Behzad Razavi:
Mutual Injection Pulling Between Oscillators. CICC 2006: 675-678 - [c23]Turgut Aytur, Han-Chang Kang, Ravishankar H. Mahadevappa, Mustafa Altintas, Stephan ten Brink, Thanh Diep, Cheng-Chung Hsu, Feng Shi, Fei-Ran Yang, Chao-Cheng Lee, Ran-Hong Yan, Behzad Razavi:
A Fully Integrated UWB PHY in 0.13µm CMOS. ISSCC 2006: 418-427 - 2005
- [j39]Jri Lee, Behzad Razavi:
Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". IEEE J. Solid State Circuits 40(2): 559 (2005) - [j38]Pengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Christopher Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gowder, Siegfried Hart, Lam Huynh, Thai Nguyen, Behzad Razavi:
A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS. IEEE J. Solid State Circuits 40(9): 1932-1939 (2005) - [j37]Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Kuang-Yu (Jason) Li, Ran-Hong (Ran) Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee:
A UWB CMOS transceiver. IEEE J. Solid State Circuits 40(12): 2555-2562 (2005) - [c22]Behzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Ran-Hong Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee:
Multiband UWB transceivers. CICC 2005: 141-148 - [c21]Hamid Rafati, Behzad Razavi:
A new receiver architecture for multiple-antenna systems. CICC 2005: 357-360 - [c20]Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget
Will continued process-node shrinks kill high-performance analog design? CICC 2005: 616-617 - [c19]Bryan D. Ackland, Behzad Razavi, Larry West:
A comparison of electrical and optical clock networks in nanometer technologies. CICC 2005: 779-782 - 2004
- [j36]Jri Lee, Behzad Razavi:
A 40-GHz frequency divider in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 39(4): 594-601 (2004) - [j35]Behzad Razavi:
A study of injection locking and pulling in oscillators. IEEE J. Solid State Circuits 39(9): 1415-1424 (2004) - [j34]Jri Lee, Kenneth S. Kundert, Behzad Razavi:
Analysis and modeling of bang-bang clock and data recovery circuits. IEEE J. Solid State Circuits 39(9): 1571-1580 (2004) - [j33]Sherif Galal, Behzad Razavi:
40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 39(12): 2389-2396 (2004) - [c18]Pengfei Zhang, Lawrence Der, Dawei Guo, Isaac Sever, Taoufik Bourdi, Chris Lam, Alireza Zolfaghari, Jess Chen, Douglas Gambetta, Baohong Cheng, Sujatha Gower, Siegfi Hart, Lam Huynh, Thai Nguyen, Behzad Razavi:
A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs. CICC 2004: 409-412 - 2003
- [j32]Behzad Razavi:
RF CMOS transceivers for cellular telephony. IEEE Commun. Mag. 41(8): 144-149 (2003) - [j31]Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. IEEE J. Solid State Circuits 38(1): 13-21 (2003) - [j30]Lawrence Der, Behzad Razavi:
A 2-GHz CMOS image-reject receiver with LMS calibration. IEEE J. Solid State Circuits 38(2): 167-175 (2003) - [j29]Alireza Zolfaghari, Behzad Razavi:
A low-power 2.4-GHz transmitter/receiver CMOS IC. IEEE J. Solid State Circuits 38(2): 176-183 (2003) - [j28]Tai-Cheng Lee, Behzad Razavi:
A stabilization technique for phase-locked frequency synthesizers. IEEE J. Solid State Circuits 38(6): 888-894 (2003) - [j27]Sherif Galal, Behzad Razavi:
10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 38(12): 2138-2146 (2003) - [j26]Jri Lee, Behzad Razavi:
A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 38(12): 2181-2190 (2003) - [j25]Pengfei Zhang, Thai Nguyen, Christopher Lam, Douglas Gambetta, Theerachet Soorapanth, Baohong Cheng, Siegfried Hart, Isaac Sever, Taoufik Bourdi, Andrew (KhongMeng) Tham, Behzad Razavi:
A 5-GHz direct-conversion CMOS transceiver. IEEE J. Solid State Circuits 38(12): 2232-2238 (2003) - [j24]Sherif Galal, Behzad Razavi:
Broadband ESD protection circuits in CMOS technology. IEEE J. Solid State Circuits 38(12): 2334-2340 (2003) - [c17]Behzad Razavi:
A study of injection pulling and locking in oscillators. CICC 2003: 305-312 - [c16]Jri Lee, Kenneth S. Kundert, Behzad Razavi:
Modeling of jitter in bang-bang clock and data recovery circuits. CICC 2003: 711-714 - 2002
- [j23]Behzad Razavi:
Challenges in the design of high-speed clock and data recovery circuits. IEEE Commun. Mag. 40(8): 94-101 (2002) - [j22]Behzad Razavi:
Prospects of CMOS technology for high-speed optical communication circuits. IEEE J. Solid State Circuits 37(9): 1135-1145 (2002) - [c15]Alireza Zolfaghari, Behzad Razavi:
A noninvasive channel-select filter for a CMOS Bluetooth receiver. CICC 2002: 341-344 - [c14]Behzad Razavi:
The role of monolithic transmission lines in high-speed integrated circuits. CICC 2002: 367-374 - 2001
- [j21]Tai-Cheng Lee, Behzad Razavi:
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. IEEE J. Solid State Circuits 36(3): 366-373 (2001) - [j20]Seema Butala Anand, Behzad Razavi:
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. IEEE J. Solid State Circuits 36(3): 432-439 (2001) - [j19]Alireza Zolfaghari, Andrew Chan, Behzad Razavi:
Stacked inductors and transformers in CMOS technology. IEEE J. Solid State Circuits 36(4): 620-628 (2001) - [j18]Jafar Savoj, Behzad Razavi:
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE J. Solid State Circuits 36(5): 761-768 (2001) - [j17]Behzad Razavi:
A 5.2-GHz CMOS receiver with 62-dB image rejection. IEEE J. Solid State Circuits 36(5): 810-815 (2001) - [c13]Tai-Cheng Lee, Behzad Razavi:
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. CICC 2001: 131-134 - [c12]Behzad Razavi:
Design of high-speed circuits for optical communication systems. CICC 2001: 315-322 - [c11]Jafar Savoj, Behzad Razavi:
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. DAC 2001: 121-126 - 2000
- [j16]Yun-Ti Wang, Behzad Razavi:
An 8-bit 150-MHz CMOS A/D converter. IEEE J. Solid State Circuits 35(3): 308-317 (2000) - [j15]Christopher Lam, Behzad Razavi:
A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology. IEEE J. Solid State Circuits 35(5): 788-794 (2000) - [c10]Alireza Zolfaghari, Andrew Chan, Behzad Razavi:
Stacked inductors and 1-to-2 transformers in CMOS technology. CICC 2000: 345-348 - [c9]Seema Butala Anand, Behzad Razavi:
A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology. CICC 2000: 379-382 - [c8]Tai-Cheng Lee, Behzad Razavi:
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. CICC 2000: 461-464
1990 – 1999
- 1999
- [j14]Behzad Razavi:
CMOS technology characterization for analog and RF design. IEEE J. Solid State Circuits 34(3): 268-276 (1999) - [j13]Behzad Razavi:
A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications. IEEE J. Solid State Circuits 34(5): 573-579 (1999) - [j12]Behzad Razavi:
A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs. IEEE J. Solid State Circuits 34(10): 1382-1385 (1999) - [c7]Yun-Ti Wang, Behzad Razavi:
An 8-bit 150-MHz CMOS A/D converter. CICC 1999: 117-120 - [c6]Behzad Razavi:
RF transmitter architectures and circuits. CICC 1999: 197-204 - 1998
- [j11]Stephen Wu, Behzad Razavi:
A 900-MHz/1.8-GHz CMOS receiver for dual-band applications. IEEE J. Solid State Circuits 33(12): 2178-2185 (1998) - [c5]Behzad Razavi:
CMOS technology characterization for analog and RF design. CICC 1998: 23-30 - [c4]Behzad Razavi:
Architectures and circuits for RF CMOS receivers. CICC 1998: 393-400 - [c3]Frank Herzel, Behzad Razavi:
Oscillator jitter due to supply and substrate noise. CICC 1998: 489-492 - [c2]Behzad Razavi:
RF IC Design Challenges. DAC 1998: 408-413 - 1997
- [j10]Behzad Razavi:
Recent advances in RF integrated circuits. IEEE Commun. Mag. 35(12): 36-43 (1997) - [j9]Behzad Razavi:
A 2-GHz 1.6-mW phase-locked loop. IEEE J. Solid State Circuits 32(5): 730-735 (1997) - [c1]Behzad Razavi:
Next-Generation RF Circuits and Systems. ARVLSI 1997: 270-283 - 1996
- [j8]Behzad Razavi:
A study of phase noise in CMOS oscillators. IEEE J. Solid State Circuits 31(3): 331-343 (1996) - [j7]Behzad Razavi:
A 2.5-Gb/s 15-mW clock recovery circuit. IEEE J. Solid State Circuits 31(4): 472-480 (1996) - 1995
- [j6]Behzad Razavi, Kwing F. Lee, Ran H. Yan:
Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS. IEEE J. Solid State Circuits 30(2): 101-109 (1995) - [j5]Behzad Razavi:
Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digital bipolar technology. IEEE J. Solid State Circuits 30(7): 724-730 (1995) - [j4]Behzad Razavi:
A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply. IEEE J. Solid State Circuits 30(12): 1326-1332 (1995) - [j3]Turgut Aytur, Behzad Razavi:
A 2-GHz, 6-mW BiCMOS frequency synthesizer. IEEE J. Solid State Circuits 30(12): 1457-1462 (1995) - 1994
- [j2]Behzad Razavi, Yusuke Ota, Robert G. Swartz:
Design techniques for low-voltage high-speed digital bipolar circuits. IEEE J. Solid State Circuits 29(3): 332-339 (1994) - [j1]Behzad Razavi, JanMye James Sung:
A 6 GHz 68 mW BiCMOS phase-locked loop. IEEE J. Solid State Circuits 29(12): 1560-1565 (1994)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-19 20:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: