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Huiyang Zhou
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2020 – today
- 2024
- [c81]Ardhi Wiratama Baskara Yudha
, Jiaqi Xue
BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-wise Comparisons. PACT 2024: 121-132 - [c80]Rahaf Abdullah, Hyokeun Lee, Huiyang Zhou
Salus: Efficient Security Support for CXL-Expanded GPU Memory. HPCA 2024: 1-15 - [c79]Peiyi Li, Ji Liu, Alvin Gonzales, Zain H. Saleem, Huiyang Zhou, Paul D. Hovland:
QuTracer: Mitigating Quantum Gate and Measurement Errors by Tracing Subsets of Qubits. ISCA 2024: 103-117 - [c78]Yuwei Jin, Zirui Li, Fei Hua, Tianyi Hao, Huiyang Zhou, Yipeng Huang, Eddy Z. Zhang:
Tetris: A Compilation Framework for VQA Applications in Quantum Computing. ISCA 2024: 277-292 - [c77]Debpratim Adak, Hyokeun Lee, Ben Feinberg, Gwendolyn Voskuilen, Clayton Hughes, Huiyang Zhou, Amro Awad:
SEFsim: A Statistically-Guided Fast DRAM Simulator. ISPASS 2024: 304-306 - [i12]Dror Baron, Hrushikesh Pramod Patil, Huiyang Zhou:
Maximum Likelihood Quantum Error Mitigation for Algorithms with a Single Correct Output. CoRR abs/2402.11830 (2024) - [i11]Ardhi Wiratama Baskara Yudha, Jiaqi Xue, Qian Lou, Huiyang Zhou, Yan Solihin:
BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-wise Comparisons. CoRR abs/2407.07308 (2024) - 2023
- [j22]Xinjian Long, Xiangyang Gong, Bo Zhang
An Intelligent Framework for Oversubscription Management in CPU-GPU Unified Memory. J. Grid Comput. 21(1): 11 (2023) - [j21]Xinjian Long, Xiangyang Gong
Deep learning based data prefetching in CPU-GPU unified virtual memory. J. Parallel Distributed Comput. 174: 19-31 (2023) - [c76]Rahaf Abdullah, Huiyang Zhou
Plutus: Bandwidth-Efficient Memory Security for GPUs. HPCA 2023: 543-555 - [c75]Alexander Freij, Huiyang Zhou
SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers. HPCA 2023: 677-690 - [c74]Peiyi Li, Ji Liu
Enhancing Virtual Distillation with Circuit Cutting for Quantum Error Mitigation. ICCD 2023: 94-101 - [c73]Yavuz Selim Tozlu, Huiyang Zhou
PBVR: Physically Based Rendering in Virtual Reality. IISWC 2023: 77-86 - [c72]Hrushikesh Pramod Patil
Folding-Free ZNE: A Comprehensive Quantum Zero-Noise Extrapolation Approach for Mitigating Depolarizing and Decoherence Noise. QCE 2023: 898-909 - [i10]Ehsan Faghih, Huiyang Zhou:
Dynamic Runtime Assertions in Quantum Ternary Systems. CoRR abs/2312.15309 (2023) - 2022
- [j20]Chen Zhao
A Survey of GPU Multitasking Methods Supported by Hardware Architecture. IEEE Trans. Parallel Distributed Syst. 33(6): 1451-1463 (2022) - [c71]Shougang Yuan, Amro Awad, Ardhi Wiratama Baskara Yudha, Yan Solihin, Huiyang Zhou
Adaptive Security Support for Heterogeneous Memory on GPUs. HPCA 2022: 213-228 - [c70]Ji Liu
Not All SWAPs Have the Same Cost: A Case for Optimization-Aware Qubit Routing. HPCA 2022: 709-725 - [c69]Peiyi Li, Ji Liu
Exploiting Quantum Assertions for Error Mitigation and Quantum Program Debugging. ICCD 2022: 124-131 - [c68]Ardhi Wiratama Baskara Yudha, Jake Meyer, Shougang Yuan, Huiyang Zhou
LITE: a low-cost practical inter-operable GPU TEE. ICS 2022: 7:1-7:13 - [i9]Xinjian Long, Xiangyang Gong, Huiyang Zhou:
Deep Learning based Data Prefetching in CPU-GPU Unified Virtual Memory. CoRR abs/2203.12672 (2022) - [i8]Xinjian Long, Xiangyang Gong, Huiyang Zhou:
An Intelligent Framework for Oversubscription Management in CPU-GPU Unified Memory. CoRR abs/2204.02974 (2022) - [i7]Ji Liu, Peiyi Li, Huiyang Zhou:
Not All SWAPs Have the Same Cost: A Case for Optimization-Aware Qubit Routing. CoRR abs/2205.10596 (2022) - 2021
- [c67]Ji Liu
Relaxed Peephole Optimization: A Novel Compiler Optimization for Quantum Circuits. CGO 2021: 301-314 - [c66]John Ravi, Tri Nguyen
PILOT: a Runtime System to Manage Multi-tenant GPU Unified Memory Footprint. HiPC 2021: 442-447 - [c65]Ji Liu
Systematic Approaches for Precise and Approximate Quantum State Runtime Assertion. HPCA 2021: 179-193 - [c64]Shougang Yuan, Yan Solihin, Huiyang Zhou:
PSSM: achieving secure memory for GPUs with partitioned and sectored security metadata. ICS 2021: 139-151 - [c63]Tim Rogers, Huiyang Zhou:
Message from the Program Chairs. IISWC 2021: ix - [c62]Shougang Yuan, Ardhi Wiratama Baskara Yudha, Yan Solihin, Huiyang Zhou
Analyzing Secure Memory Architecture for GPUs. ISPASS 2021: 59-69 - [c61]Alexander Freij, Huiyang Zhou, Yan Solihin:
Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent Memory. MICRO 2021: 1227-1240 - [e1]Huiyang Zhou, Jose Moreira, Frank Mueller, Yoav Etsion:
ICS '21: 2021 International Conference on Supercomputing, Virtual Event, USA, June 14-17, 2021. ACM 2021, ISBN 978-1-4503-8335-6 [contents] - 2020
- [j19]Yonghua Mao
Exploring Convolution Neural Network for Branch Prediction. IEEE Access 8: 152008-152016 (2020) - [j18]Chen Zhao, Wu Gao, Feiping Nie, Fei Wang
Fair and cache blocking aware warp scheduling for concurrent kernel execution on GPU. Future Gener. Comput. Syst. 112: 1093-1105 (2020) - [c60]Ji Liu
Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. ASPLOS 2020: 1017-1030 - [c59]Ji Liu
MKPipe: a compiler framework for optimizing multi-kernel workloads in OpenCL for FPGA. ICS 2020: 39:1-39:12 - [c58]Ji Liu
Reliability Modeling of NISQ- Era Quantum Computers. IISWC 2020: 94-105 - [c57]Ardhi Wiratama Baskara Yudha, Keiji Kimura, Huiyang Zhou
Scalable and Fast Lazy Persistency on GPUs. IISWC 2020: 252-263 - [c56]Alexander Freij, Shougang Yuan, Huiyang Zhou, Yan Solihin:
Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory. MICRO 2020: 14-27 - [c55]Huiyang Zhou, Haoyan Liu, Zhao Yan, Yunbo Cao, Zhoujun Li:
LARQ: Learning to Ask and Rewrite Questions for Community Question Answering. NLPCC (2) 2020: 318-330 - [i6]Ji Liu, Abdullah-Al Kafi, Xipeng Shen, Huiyang Zhou:
MKPipe: A Compiler Framework for Optimizing Multi-Kernel Workloads in OpenCL for FPGA. CoRR abs/2002.01614 (2020) - [i5]Alexander Freij, Shougang Yuan, Huiyang Zhou, Yan Solihin:
Streamlining Integrity Tree Updates for Secure Persistent Non-Volatile Memory. CoRR abs/2003.04693 (2020) - [i4]Ji Liu, Luciano Bello, Huiyang Zhou:
Relaxed Peephole Optimization: A Novel Compiler Optimization for Quantum Circuits. CoRR abs/2012.07711 (2020)
2010 – 2019
- 2019
- [j17]Huiyang Zhou
Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. IEEE Comput. Archit. Lett. 18(2): 111-114 (2019) - [j16]Zhen Lin
Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution. ACM Trans. Archit. Code Optim. 16(3): 23:1-23:27 (2019) - [c54]Zhen Lin
Exploring Memory Persistency Models for GPUs. PACT 2019: 311-323 - [c53]Zhen Lin
Scatter-and-Gather Revisited: High-Performance Side-Channel-Resistant AES on GPUs. GPGPU@ASPLOS 2019: 2-11 - [c52]Hui Guan, Lin Ning, Zhen Lin, Xipeng Shen, Huiyang Zhou, Seung-Hwan Lim:
In-Place Zero-Space Memory Protection for CNN. NeurIPS 2019: 5735-5744 - [i3]Zhen Lin, Mohammad A. Alshboul, Yan Solihin, Huiyang Zhou:
Exploring Memory Persistency Models for GPUs. CoRR abs/1904.12661 (2019) - [i2]Hui Guan, Lin Ning, Zhen Lin, Xipeng Shen, Huiyang Zhou, Seung-Hwan Lim:
In-Place Zero-Space Memory Protection for CNN. CoRR abs/1910.14479 (2019) - 2018
- [j15]Zhen Lin
GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP. ACM Trans. Archit. Code Optim. 15(1): 15:1-15:21 (2018) - [c51]Hongwen Dai, Zhen Lin
Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls. HPCA 2018: 208-220 - 2017
- [c50]Hongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang
POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls. PACT 2017: 144-145 - [c49]Anshuman Verma, Huiyang Zhou
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs. DAC 2017: 56:1-56:6 - [c48]Guoyang Chen, Yue Zhao, Xipeng Shen
EffiSha: A Software Framework for Enabling Effficient Preemptive Scheduling of GPU. PPoPP 2017: 3-16 - 2016
- [j14]Yunquan Zhang, Shigang Li, Shengen Yan, Huiyang Zhou
A Cross-Platform SpMV Framework on Many-Core Architectures. ACM Trans. Archit. Code Optim. 13(4): 33:1-33:25 (2016) - [c47]Guoyang Chen, Huiyang Zhou
OpenCL-based erasure coding on heterogeneous architectures. ASAP 2016: 33-40 - [c46]Hongwen Dai, Chao Li, Huiyang Zhou
A model-driven approach to warp/thread-block level GPU cache bypassing. DAC 2016: 94:1-94:6 - [c45]Qi Jia, Huiyang Zhou
Tuning Stencil codes in OpenCL for FPGAs. ICCD 2016: 249-256 - [c44]Chen Zhao, Fei Wang, Zhen Lin, Huiyang Zhou
Selectively GPU Cache Bypassing for Un-Coalesced Loads. ICPADS 2016: 908-915 - [c43]Chao Li, Yi Yang, Min Feng, Srimat T. Chakradhar, Huiyang Zhou
Optimizing memory efficiency for deep convolutional neural networks on GPUs. SC 2016: 633-644 - [c42]Zhen Lin
Enabling efficient preemption for SIMT architectures with lightweight context switching. SC 2016: 898-908 - [i1]Chao Li, Yi Yang, Min Feng, Srimat T. Chakradhar, Huiyang Zhou:
Optimizing Memory Efficiency for Deep Convolutional Neural Networks on GPUs. CoRR abs/1610.03618 (2016) - 2015
- [j13]Yi Yang, Chao Li
CUDA-NP: Realizing Nested Thread-Level Parallelism in GPGPU Applications. J. Comput. Sci. Technol. 30(1): 3-19 (2015) - [c41]Paul D. Franzon
Computing in 3D. 3DIC 2015: TS6.1.1-TS6.1.2 - [c40]Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou
Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture. CCGRID 2015: 121-130 - [c39]Chao Li
Automatic data placement into GPU on-chip memory resources. CGO 2015: 23-33 - [c38]Paul D. Franzon
Computing in 3D. CICC 2015: 1-6 - [c37]Saurabh Gupta, Huiyang Zhou
Spatial Locality-Aware Cache Partitioning for Effective Cache Sharing. ICPP 2015: 150-159 - [c36]Chao Li
Locality-Driven Dynamic GPU Cache Bypassing. ICS 2015: 67-77 - [c35]Kothiya Mayank, Hongwen Dai, Jizeng Wei, Huiyang Zhou
Analyzing graphics processor unit (GPU) instruction set architectures. ISPASS 2015: 155-156 - 2014
- [c34]Paul D. Franzon
3D-enabled customizable embedded computer (3DECC). 3DIC 2014: 1-3 - [c33]Ping Xiang, Yi Yang, Huiyang Zhou
Warp-level divergence in GPUs: Characterization, impact, and mitigation. HPCA 2014: 284-295 - [c32]Yi Yang, Ping Xiang, Michael Mantor, Norman Rubin, Lisa R. Hsu, Qunfeng Dong, Huiyang Zhou
A Case for a Flexible Scalar Unit in SIMT Architecture. IPDPS 2014: 93-102 - [c31]Chao Li
Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs. ISPASS 2014: 231-242 - [c30]Yi Yang, Huiyang Zhou
CUDA-NP: realizing nested thread-level parallelism in GPGPU applications. PPoPP 2014: 93-106 - [c29]Shengen Yan, Chao Li
yaSpMV: yet another SpMV framework on GPUs. PPoPP 2014: 107-118 - [c28]Hongwen Dai, Christos Kartsaklis, Chao Li, Tomislav Janjusic, Huiyang Zhou:
RACB: Resource Aware Cache Bypass on GPUs. SBAC-PAD (Workshops) 2014: 24-29 - [p1]Yi Yang, Huiyang Zhou
A Highly Efficient FFT Using Shared-Memory Multiplexing. Numerical Computations with GPUs 2014: 363-377 - 2013
- [j12]Yi Yang, Huiyang Zhou
The Implementation of a High Performance GPGPU Compiler. Int. J. Parallel Program. 41(6): 768-781 (2013) - [j11]Saurabh Gupta, Ping Xiang, Yi Yang, Huiyang Zhou
Locality principle revisited: A probability-based quantitative approach. J. Parallel Distributed Comput. 73(7): 1011-1027 (2013) - [j10]Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou
Architecting against Software Cache-Based Side-Channel Attacks. IEEE Trans. Computers 62(7): 1276-1288 (2013) - [c27]Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Lisa R. Hsu, Huiyang Zhou
Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement. ICS 2013: 433-442 - [c26]Saurabh Gupta, Hongliang Gao, Huiyang Zhou
Adaptive Cache Bypassing for Inclusive Last Level Caches. IPDPS 2013: 1243-1253 - [c25]Saurabh Gupta, Ping Xiang, Huiyang Zhou
Analyzing locality of memory references in GPU architectures. MSPC@PLDI 2013: 12:1-12:2 - 2012
- [j9]Yi Yang, Ping Xiang, Jingfei Kong, Mike Mantor, Huiyang Zhou
A unified optimizing compiler framework for different GPGPU architectures. ACM Trans. Archit. Code Optim. 9(2): 9:1-9:33 (2012) - [c24]Yi Yang, Ping Xiang, Mike Mantor, Norm Rubin, Huiyang Zhou:
Shared memory multiplexing: a novel way to improve GPGPU throughput. PACT 2012: 283-292 - [c23]Ping Xiang, Yi Yang, Mike Mantor, Norm Rubin, Huiyang Zhou:
Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing. PACT 2012: 449-450 - [c22]Yi Yang, Ping Xiang, Mike Mantor, Huiyang Zhou:
CPU-assisted GPGPU on fused CPU-GPU architectures. HPCA 2012: 103-114 - [c21]Yi Yang, Ping Xiang, Mike Mantor, Huiyang Zhou
Fixing Performance Bugs: An Empirical Study of Open-Source GPGPU Programs. ICPP 2012: 329-339 - [c20]Saurabh Gupta, Ping Xiang, Yi Yang, Huiyang Zhou
Locality Principle Revisited: A Probability-Based Quantitative Approach. IPDPS 2012: 995-1009 - 2011
- [j8]Martin Dimitrov, Huiyang Zhou:
Combining Local and Global History for High Performance Data Prefetching. J. Instr. Level Parallelism 13 (2011) - [c19]Martin Dimitrov, Huiyang Zhou
Time-Ordered Event Traces: A New Debugging Primitive for Concurrency Bugs. IPDPS 2011: 311-321 - 2010
- [c18]Jingfei Kong, Martin Dimitrov, Yi Yang, Janaka Liyanage, Lin Cao, Jacob Staples, Mike Mantor, Huiyang Zhou
Accelerating MATLAB Image Processing Toolbox functions on GPUs. GPGPU 2010: 75-85 - [c17]Jingfei Kong, Huiyang Zhou
Improving privacy and lifetime of PCM-based main memory. DSN 2010: 333-342 - [c16]Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou
A GPGPU compiler for memory optimization and parallelism management. PLDI 2010: 86-97 - [c15]Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou
An optimizing compiler for GPGPU programs with input-data sharing. PPoPP 2010: 343-344
2000 – 2009
- 2009
- [c14]Martin Dimitrov, Huiyang Zhou
Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging. ASPLOS 2009: 61-72 - [c13]Martin Dimitrov, Mike Mantor, Huiyang Zhou
Understanding software approaches for GPGPU reliability. GPGPU 2009: 94-104 - [c12]Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou
Hardware-software integrated approaches to defend against software cache-based side channel attacks. HPCA 2009: 393-404 - 2008
- [c11]Jingfei Kong, Onur Aciiçmez, Jean-Pierre Seifert, Huiyang Zhou
Deconstructing new cache designs for thwarting software cache-based side channel attacks. CSAW 2008: 25-34 - [c10]Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zhou
Address-branch correlation: A novel locality for long-latency hard-to-predict branches. HPCA 2008: 74-85 - 2007
- [j7]Hongliang Gao, Huiyang Zhou:
PMPM: Prediction by Combining Multiple Partial Matches. J. Instr. Level Parallelism 9 (2007) - [j6]Yi Ma, Hongliang Gao, Martin Dimitrov, Huiyang Zhou:
Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery. IEEE Trans. Parallel Distributed Syst. 18(8): 1080-1093 (2007) - [c9]Martin Dimitrov, Huiyang Zhou:
Unified Architectural Support for Soft-Error Protection or Software Bug Detection. PACT 2007: 73-82 - 2006
- [j5]Huiyang Zhou:
A case for fault tolerance and performance enhancement using chip multi-processors. IEEE Comput. Archit. Lett. 5(1): 22-25 (2006) - [j4]Yi Ma, Hongliang Gao, Huiyang Zhou:
Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables. IEEE Trans. Computers 55(8): 1057-1061 (2006) - [c8]Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou
Improving software security via runtime instruction-level taint checking. ASID 2006: 18-24 - [c7]Yi Ma, Huiyang Zhou
Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. ICCD 2006: 120-126 - 2005
- [j3]Hongliang Gao, Huiyang Zhou:
Adaptive Information Processing: An Effective Way to Improve Perceptron Predictors. J. Instr. Level Parallelism 7 (2005) - [j2]Huiyang Zhou
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. IEEE Trans. Computers 54(7): 897-912 (2005) - [c6]Huiyang Zhou
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window. IEEE PACT 2005: 231-242 - 2003
- [j1]Huiyang Zhou
Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Syst. 2(3): 347-372 (2003) - [c5]Huiyang Zhou, Thomas M. Conte
Enhancing memory level parallelism via recovery-free value prediction. ICS 2003: 326-335 - [c4]Huiyang Zhou
Detecting Global Stride Locality in Value Streams. ISCA 2003: 324-335 - 2002
- [c3]Huiyang Zhou
Code Size Efficiency in Global Scheduling for ILP Processors. Interaction between Compilers and Computer Architectures 2002: 79-90 - 2001
- [c2]Huiyang Zhou
Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61-70 - [c1]Huiyang Zhou
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. LCPC 2001: 223-238
Coauthor Index
Mike Mantor
aka: Michael Mantor
aka: Michael Mantor
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last updated on 2024-10-23 20:35 CEST by the dblp team
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