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CICC 2012: San Jose, California, USA
- Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012. IEEE 2012, ISBN 978-1-4673-1555-5
Behavioral Modeling for RF and AMS
- Colin C. McAndrew, Brian Chen:
Behavioral modeling for RF and AMS. 1 - David E. Root, Jianjun Xu, Franz Sischka, Mihai Marcu, Jason Horn, R. M. Biernacki, Masaya Iwamoto:
Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trends. 1-6 - Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim:
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. 1-4 - Nagib Hakim, A. Bhaduri, K. Donepudi, S. Bodapati:
A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation. 1-5
RF & mm Wave Power Amplifiers and Transmitters
- Mehran M. Izad, Chun-Huat Heng
:
A 17pJ/bit 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applications. 1-4 - Peter M. Asbeck, Lawrence E. Larson, Donald F. Kimball, James F. Buckwalter:
CMOS handset power amplifiers: Directions for the future. 1-6 - Anandaroop Chakrabarti, Harish Krishnaswamy:
High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS. 1-4 - Kunal Datta, Jonathan Roderick, Hossein Hashemi:
A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAE. 1-4
Analog Techniques
- Don Thelen, Xicheng Jiang:
Analog Techniques. 1 - Julie R. Hu, Richard C. Ruby, Brian P. Otis:
A 1.5GHz 0.2psRMS jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOS. 1-4 - Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh:
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS. 1-4 - Pio Balmelli, John M. Khoury, Eduardo Viegas, Paulo Santos, Vitor Pereira:
Linearization of class D amplifiers. 1-4 - William Biederman, Daniel J. Yeager, Elad Alon, Jan M. Rabaey:
A CMOS switched-capacitor fractional bandgap reference. 1-4
Modeling & Design for Variability and Reliability
- Trent McConaghy, Hidetoshi Onodera:
Modeling & design for variability and reliability. 1-2 - Xin Li, Wangyang Zhang, Fa Wang:
Large-scale statistical performance modeling of analog and mixed-signal circuits. 1-8 - Georges G. E. Gielen
Designing reliable analog circuits in an unreliable world. 1-4 - Jyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano
Statistical aging under dynamic voltage scaling: A logarithmic model approach. 1-4 - Bo Yu, Xin Li, James Yonemura, Zhiyuan Wu, Jung-Suk Goo, Ciby Thuruthiyil, Ali Icel:
Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables. 1-4 - Kiyohiko Sakakibara, Toshio Kumamoto, K. Arimoto:
Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regions. 1-4
High-Speed Wireline Transceivers and Clocking
- Gerrit den Besten, Shunichi Kaeriyama:
High-speed wireline transceivers and clocking. 1-2 - Amer Samarah, Anthony Chan Carusone
A digital phase-locked loop with calibrated coarse and stochastic fine TDC. 1-4 - Dustin Dunwell, Anthony Chan Carusone
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. 1-4 - Namik Kocaman, Siavash Fallahi, Mahyar Kargar, Mehdi Khanpour, Afshin Momtaz:
An 8.5-11.5Gbps SONET transceiver with referenceless frequency acquisition. 1-4 - Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe:
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. 1-4 - Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang:
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. 1-4 - Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon:
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS. 1-4 - Ehsan Zhian Tabasy, Ayman Shafik, S. Huang, N. Yang, Sebastian Hoyos, Samuel Palermo:
A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS. 1-4 - Jean-Olivier Plouchart, Mihai A. T. Sanduleanu
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. 1-4 - Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. 1-4
Radio Receiver Techniques
- Alberto Valdes-Garcia, Ramesh Harjani:
Radio receiver techniques. 1 - Aslam A. Rafi, T. R. Viswanathan:
Clock-gated harmonic rejection mixers. 1-8 - Ray Gomez, Hanli Zou, Binning Chen, Bruce Currivan, Dave (Sung-Hsien) Chang:
A Full-Band processor for reduction of RF mixer LO harmonic images. 1-4 - Satwik A. Patnaik, Sachin Kalia, Bodhisatwa Sadhu
An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS. 1-4 - Alyosha C. Molnar, Caroline Andrews:
Impedance, filtering and noise in n-phase passive CMOS mixers. 1-8 - Jianjun Yu, Feng Zhao, Joseph Cali, Desheng Ma, Xueyang Geng, Fa Foster Dai, J. David Irwin, Andre Aklian:
A single-chip x-band chirp radar MMIC with stretch processing. 1-4 - Lechang Liu, Hiroki Ishikuro, Tadahiro Kuroda:
A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. 1-4
Advances in 3D Design and Optimization
- Steven J. E. Wilton, Visvesh S. Sathe:
Advances in 3D design and optimization. 1 - Arifur Rahman, Hong Shi, Zhe Li, Dale Ibbotson, Sesh Ramaswami:
Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs). 1-8 - Thorlindur Thorolfsson, Steve Lipa, Paul D. Franzon
A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration. 1-4 - Sangwook Han, David D. Wentzloff:
0.61W/mm2 resonant inductively coupled power transfer for 3D-ICs. 1-4
PLLs, VCOs, and Dividers
- Fa Foster Dai, Howard C. Luong:
PLLs, VCOs, and dividers. 1-2 - Seungjin Kim, In-Young Lee, Joo-Myoung Kim, Sang-Gug Lee:
A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration. 1-4 - Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. 1-4 - Liang Wu, Howard C. Luong
A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency divider. 1-4 - Andrea Ghilioni, Ugo Decanis, Andrea Mazzanti, Francesco Svelto:
A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz. 1-4 - Anna Moroni, Raffaella Genesi, Danilo Manstretta
A distributed "hybrid" wave oscillator array for millimeter-wave phased-arrays. 1-4 - Jun Yin
A 57.5-to-90.1GHz magnetically-tuned multi-mode CMOS VCO. 1-4 - Yiwu Tang, Jianyun Hu, Jongmin Park, Jaehyouk Choi
A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation. 1-4
Biomedical and Sensors
- Emmanuel Quevy, Pedram Mohseni:
Biomedical and sensors. 1 - Edward K. F. Lee:
A feedback controlled coil driver for transcutaneous power transmission. 1-4 - Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy. 1-4 - Sunjoo Hong, Seulki Lee, Taehwan Roh, Hoi-Jun Yoo:
A 46 μW motion artifact reduction bio-signal sensor with ICA based adaptive DC level control for sleep monitoring system. 1-4 - Gyouho Kim, Yoonmyung Lee
A 695 pW standby power optical wake-up receiver for wireless sensor nodes. 1-4 - Albert Wang, Sriram Sivaramakrishnan, Alyosha C. Molnar:
A 180nm CMOS image sensor with on-chip optoelectronic image compression. 1-4 - Xiaotie Wu, Milin Zhang, Nader Engheta, Jan Van der Spiegel:
Design of a monolithic CMOS image sensor integrated focal plane wire-grid polarizer filter mosaic. 1-4
High Speed Data Converters
- Eric Naviasky, Mohammad Ranjbar:
High-speed data converters. 1 - Sedigheh Hashemi, Behzad Razavi:
A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion. 1-4 - Yuji Nakajima, Norihito Kato, Akemi Sakaguchi, Toshio Ohkido, Kenji Shimomaki, Hiroko Masuda, Chikahiro Shiroma, Michio Yotsuyanagi, Takahiro Miki:
A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration. 1-4 - Hyeok-Ki Hong, Wan Kim
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. 1-4 - Jiangfeng Wu, Chun-Ying Chen, Tianwei Li, Wenbo Liu, Lin He, Shauhyuarn Sean Tsai, Binning Chen, Chun-Sheng Huang, Juo-Jung Hung, Wei-Ta Shih, Hing T. Hung, Steven Jaffe, Loke Tan, Hung Vu:
A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization. 1-4 - Behzad Razavi:
Problem of timing mismatch in interleaved ADCs. 1-8
Advanced IC Technologies I
- Alvin Loke, David A. Sunderland:
Advanced IC technologies I. 1 - Chris Auth:
22-nm fully-depleted tri-gate CMOS transistors. 1-6 - Anthony S. Oates:
Reliability challenges for the continued scaling of IC technologies. 1-4 - Ali Khaki-Firooz, Kangguo Cheng, Qing Liu, Toshiharu Nagumo, Nicolas Loubet, Alexander Reznicek, James Kuss, J. Gimbert, Raghavasimhan Sreenivasan, Maud Vinet, Laurent Grenouillet, Yannick Le Tiec, Romain Wacquez, Z. Ren, J. Cai, Davood Shahrjerdi, Prasanna Kulkarni, Shom Ponoth, Scott Luning, Bruce Doris:
Extremely thin SOI for system-on-chip applications. 1-4 - Carl-Mikael Zetterling
Present and future applications of Silicon Carbide devices and circuits. 1-8
Advanced Memory Topics
- Vikas Chandra, Tom Andre:
Advanced memory topics. 1 - Rakesh Gnana David Jeyasingh, Jiale Liang, Marissa Caldwell, Duygu Kuzum, H.-S. Philip Wong:
Phase Change Memory: Scaling and applications. 1-7 - Suk-Soo Pyo, Jun-Sung Kim, Jung-Han Kim, Hyun-Taek Jung, Taejoong Song, Cheol-Ha Lee, Gyun-Hong Kim, Young-Keun Lee, Kee Sup Kim:
A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology. 1-4 - Wei Zhang, Ki Chul Chun, Chris H. Kim:
A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode. 1-4 - Min Huang, Moty Mehalel, Ramesh Arvapalli, Songnian He:
An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family. 1-4 - Mudit Bhargava, Cagla Cakir, Ken Mai
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. 1-4
Power Management
- William McIntyre, Christoph Sandner
Power management. 1 - Yingzhe Hu, Warren Rieutort-Louis, Liechao Huang, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
Flexible solar-energy harvesting system on plastic with thin-film LC oscillators operating above ft for inductively-coupled power delivery. 1-4 - Suyoung Bang, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems. 1-4 - Massimo Alioto, Elio Consoli, Jan M. Rabaey:
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS. 1-4 - Sudhir S. Kudva, Ramesh Harjani:
Fully integrated capacitive converter with all digital ripple mitigation. 1-4 - Han Peng, David I. Anderson, Mona Mostafa Hella:
A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technology. 1-4 - Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. 1-4 - Y. H. Ko, Y. S. Jang, S. K. Han, S. G. Lee:
Non-load-balance-dependent high efficiency single-inductor multiple-output (SIMO) DC-DC converters. 1-4 - William Lepkowski, Seth J. Wilk, M. Reza Ghajar, Bertan Bakkaloglu
An integrated MESFET voltage follower LDO for high power and PSR RF and analog applications. 1-4
Energy Efficient Architecture and Enabling Technology for Advanced SoCs
- Arifur Rahman, Lawrence Clark:
Energy-efficient architecture and enabling technology for advanced SOCs. 1-2 - Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber:
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. 1-4 - Junyoung Park, Injoon Hong, Gyeonghoon Kim, Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo:
Online Reinforcement Learning NoC for portable HD object recognition processor. 1-4 - Behrooz Javid, Payam Heydari:
A 4-bit 12GS/s data acquisition System-on-Chip including a flash ADC and 4-channel DeMUX in 130nm CMOS. 1-4 - Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim:
A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing. 1-4 - Arijit Raychowdhury, Carlos Tokunaga
A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. 1-4 - Zhiyoong Foo, David Devescery, Mohammad Hassan Ghaed, Inhee Lee, Abishek Madhavan, Youn Sung Park, Aswin S. Rao, Zach Renner, Nathan Roberts, Aaron Schulman, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, Thomas Schmid, Prabal Dutta, Peter M. Chen, David T. Blaauw:
A low-cost audio computer for information dissemination among illiterate people groups. 1-4 - Michal Rakowski, Julien Ryckaert, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert
Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator. 1-6
Advanced IC Technologies II
- Terence B. Hook:
Fully depleted devices for designers: FDSOI and FinFETs. 1-7 - Dick James:
Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k, metal-gate CPU. 1-4 - Jongwook Kye, Yuansheng Ma, Lei Yuan, Yunfei Deng, Harry J. Levinson:
Lithography and design integration - New paradigm for the technology architecture development. 1-4
Design Solutions for 3D Integration and Signal Integrity
- Yu Cao, Siva Mudanai:
Design solutions for 3D integration and signal integrity. 1 - Young-Joon Lee, Inki Hong, Sung Kyu Lim
Slew-aware buffer insertion for through-silicon-via-based 3D ICs. 1-8 - Jaemin Kim, Sunyoung Kim, Julien Ryckaert, Mikael Detalle, Nele Van Hoovels, Pol Marchal:
A calibrated pathfinding model for signal integrity analysis on interposer. 1-4 - Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. 1-4 - Michael G. Khazhinsky, Shuqing Cao, Harald Gossner
Electronic design automation (EDA) solutions for ESD-robust design and verification. 1-8
Data Converter Techniques
- Ron Kapusta, Yuji Nakajima:
Data converter techniques. 1 - Timir Nandi, Karthikeya Boominathan, Shanthi Pavan:
A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC. 1-4 - Xiong Zhou, Qiang Li:
A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS. 1-4 - Wenbo Liu, Pingli Huang, Yun Chiu
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. 1-4 - Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. 1-4 - R. Vitek, E. Gordon, S. Maerkovich, A. Beidas:
A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction. 1-4 - Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. 1-4
Forum Session - Silicon-based THz Circuits, Systems and Applications
- Alberto Valdes-Garcia:
Silicon-based THz circuits, systems and applications (Forum). 1
Tutorial - Power Delivery: Droop, Jitter, Test and Debug Story
- Mike Li, Manoj Sachdev:
Power delivery: Droop, jitter, test and debug story (Tutorial). 1
Poster Sessions
- Aatmesh Shrivastava, Benton H. Calhoun:
A 150nW, 5ppm/o C, 100kHz On-Chip clock source for ultra low power SoCs. 1-4 - Joseph Hamilton, Shouli Yan, T. R. Viswanathan:
An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC. 1-4 - Jayanth Kuppambatti, Peter R. Kinget
A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS. 1-4 - Hyunsoo Ha
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling. 1-4 - Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada:
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. 1-4 - Mathieu Guerin, Emmanuel Bergeret
Design of organic complementary circuits for RFID tags application. 1-4 - Aritra Dey, David R. Allee:
Amorphous silicon 5 bit flash analog to digital converter. 1-4 - Yousef Shakhsheer, Yanqing Zhang, Brian P. Otis, Benton H. Calhoun:
A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS. 1-4 - Tae-Hwang Kong, Sung-Wan Hong, Sungwoo Lee, Jong-Pil Im, Gyu-Hyeong Cho:
A 0.791mm2 fully on-chip controller with self-error-correction for boost DC-DC converter based on Zero-Order Control. 1-4 - Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger:
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. 1-4 - Kazuki Fukuoka, Ryo Mori, A. Kato, Motoshige Igarashi, Koji Shibutani, T. Yamaki, Shinji Tanaka, Koji Nii, Sadayuki Morita, Takao Koike, Noriaki Sakamoto:
A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology. 1-4 - Pierce Chuang, David Li, Manoj Sachdev, Vincent C. Gaudet
A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS. 1-4 - Mitsuhiko Igarashi
28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization. 1-4 - Jian Liu, Zitao Shi, Xin Wang, Hui Zhao, L. Wang, Chen Zhang, Zongyu Dong, L. Lin, Albert Z. Wang, Yuhua Cheng, Bin Zhao:
Field programmable SONOS ESD protection design. 1-4 - Minki Cho, Muhammad M. Khellah
Characterization of Inverse Temperature Dependence in logic circuits. 1-4 - Chiang-Hua Yeh, Han-Chi Hsieh, Peng Xu, Sudipto Chakraborty:
Multi-band, multi-mode, low-power CMOS receiver front-end for sub-GHz ISM/SRD band with narrow channel spacing. 1-4 - Keisuke Ueda, Toshiya Uozumi, Ryo Endo, Takahiro Nakamura, Tetsuya Heima, Hisayasu Sato:
A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitter. 1-4 - Sandipan Kundu, Ahmad Khairi, Jeyanandh Paramesh:
A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communication. 1-4 - Ming-Shuan Chen, Chih-Kong Ken Yang:
A low-power highly multiplexed parallel PRBS generator. 1-4 - Adam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag:
FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. 1-4 - Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. 1-4 - Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy
Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors. 1-4 - Junjie Lu, Jeremy Holleman:
A wideband ultra-low-current on-chip ammeter. 1-4 - Paul M. Furth, Sri Harsh Pakala, Annajirao Garimella, Chaitanya Mohan:
A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation. 1-4 - Jaehyup Kim, Bruce Hammer, Ramesh Harjani:
A 5-300MHz CMOS transceiver for multi-nuclear NMR spectroscopy. 1-4 - Rami A. Abdallah, Naresh R. Shanbhag:
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. 1-4 - Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki:
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. 1-4 - Cagla Cakir, Mudit Bhargava, Ken Mai
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. 1-4 - Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. 1-4 - Tzu-Chi Huang, Ming-Jhe Du, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ruei-Hong Peng, Ke-Horng Chen
Non-invasion power monitoring with 120% harvesting energy improvement by maximum power extracting control for high sustainability power meter system. 1-4 - Sriramkumar Venugopalan, Krishnanshu Dandu, Samuel Martin, Richard Taylor, Claude Cirba, Xin Zhang, Ali M. Niknejad, Chenming Hu:
A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6. 1-4 - Jun Luo, Lei Zhang, Yan Wang:
A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applications. 1-4 - Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor:
Modeling the response of Bang-Bang digital PLLs to phase error perturbations. 1-4 - Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi
A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition. 1-4 - Craig Schlottmann, Stephen Nease, Samuel A. Shapero, Paul E. Hasler:
A mixed-mode FPAA SoC for analog-enhanced signal processing. 1-4 - Xinwang Zhang, Yun Yin, Meng Cao, Zhigang Sun, Ling Fu, Zhaokang Xia, Hongxing Feng, Xing Zhang, Baoyong Chi, Ming Xu, Zhihua Wang:
A 0.1~4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS. 1-4 - Jiao Cheng, Lingli Xia, Chao Ma, Yong Lian
A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting. 1-4 - Guansheng Li, Ehsan Afshari:
A low-phase-noise wide-tuning-range quadrature oscillator in 65nm CMOS. 1-4 - Myeong-Jae Park, Hanseok Kim, Seuk Son, Jaeha Kim:
A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection. 1-4 - Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe:
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS. 1-4
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