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11th ASICON 2015: Chengdu, China
- 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015. IEEE 2015, ISBN 978-1-4799-8483-1
- Xiangliang Jin, Manfang Tian, Zhenyu Jiang, Han Wang:
A physical model of novel UV and blue-extended photodetector based on CMOS process. 1-4 - Chong Guo, Hong Zhang, Zhouyi Ma, Jie Zhang, Jie Lin, Ruizhi Zhang:
An inductive wireless telemetry circuit with OOK modulation for implantable cardiac pacemakers. 1-4 - Carol Rouying Zhan, Changsoo Hong, Jean-Philippe Lainé, Patrice Besse:
Development of high-voltage ESD protection devices on smart power technologies for automotive applications. 1-4 - Tukasa Ikeda, Makoto Ikeda:
Comprehensive study on higher order radix RSA cryptography engine. 1-4 - Jintao Li, Ming Liu, Hong Chen, Zhihua Wang:
A 0.3V-to-1.1V standard cell library in 40nm CMOS. 1-4 - Xiang Liang, Ligang Hou, Jinhui Wang, Chunhui Yang, Deyang Gao, Lin Zhu:
Transaction level model of HDMI transmitter based on System Verilog. 1-4 - Yong Lian
:
Challenges in the design of self-powered wearable wireless sensors for healthcare Internet-of-Things. 1-4 - Jipan Huang, Fang Gao, Xin'an Wang, Hongying Chen:
Ultra low power circuits design based on III-V group heterojunction tunnel field effect transistor. 1-4 - Yang Li, Hang Zhou
Design consideration of uni-traveling carrier photodiode: Influence of doping profile and buffer layer. 1-4 - Sujuan Liu, Haixiao Ma, Jiashuai Cui:
Adaptive semiblind background calibration of timing mismatches in an M-channel time-interleaved analog-to-digital converter. 1-4 - Jincheng Yang, Zhao Zhang, Peng Feng, Liyuan Liu, Nanjian Wu:
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. 1-4 - Hongyi Wang, Yanjiao Du, Xu Jia, Youyou Fan:
A low-power continuous-time comparator with enhanced bias current at the flip point. 1-4 - Dan Liu, Feng Gao, Liguang Hao:
Low noise design of 32-channel snapshot X-ray readout IC. 1-4 - Xi Tan, Sizheng Chen, Zhibin Xiao, Feng Chen, Junyu Wang:
A low power potentiostat for implantable glucose sensor tag. 1-4 - Tao Wu:
Elliptic curve GF (p) point multiplier by dual arithmetic cores. 1-4 - Zong Yang, Hui Xu, Nan Li, Zhaolin Sun:
FPGA logic design of SATA3.0 physical layer. 1-4 - Chen Zhao, Kuizhi Mei, Fei Wang
A high-efficient floating point coprocessor for SPARC Leon2 embedded processor. 1-4 - Peng Siew Chew, Kiat Seng Yeo
A 57 to 66 GHz novel six-port correlator. 1-4 - Bing Lyu, Yun Yin, Xiaobao Yu, Baoyong Chi:
A 0.1-1.5G SDR transmitter with two-stage harmonic rejection power mixer in 65-nm CMOS. 1-4 - Yongsheng Wang, Min Wang, Huaixin Xian, Yunfei Du, Bei Cao, Xiaowei Liu:
Influence of substrate coupling noise to clock and data recovery. 1-4 - Zhi Zeng, Kaidi Zhang, Wei Wang, Weijiang Xu, Jia Zhou:
Smartphone-controlled electro-wetting on dielectric microfluidics. 1-4 - Yunhui Ling, Fang Liu, Ying Zhang:
Realization of intelligent optimization algorithm on IP cores partition for NoC testing. 1-4 - Guangxing Wan, Tianli Duan, Shuxiang Zhang, Lingli Jiang, Bo Tang, Chao Zhao, Huilong Zhu, Hongyu Yu:
Overshoot stress impact on HfO2 high-κ layer dynamic SILC. 1-4 - D. J. Yu, Qi Yu, Ning Ning, Y. Liu, Z. Y. Shi:
Hybrid LED driver for multi-channel output with high consistency. 1-4 - Weizhen Wang, Jun Han, Jielin Wang, Xiaoyang Zeng:
A SIMD multiplier-accumulator design for pairing cryptography. 1-4 - Chuangwei Li, Jiancheng Li, Jianfei Wu, Yu Xiao:
Investigation on the immunity of microcontroller to electrical fast transients. 1-4 - Heyi Hu, Chun Zhang, Yongming Li:
A new method for demodulation of FSK signal with severe impulse interference. 1-4 - Zhong-Shan Zheng, Zhen-Tao Li, Ning Qiao, Kai Zhao, Fang Yu, Jia-Jun Luo
Comparison of decoupling resistors and capacitors for increasing the single event upset resistance of SRAM cells. 1-3 - Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
Employing the mixed FBB/RBB in the design of FinFET logic gates. 1-4 - Ligang Hou, Jingyan Fu, Jinhui Wang, Na Gong, Wei Zhao, Shuqin Geng:
A thermal-aware distribution method of TSV in 3D IC. 1-3 - Guangxi Hu, Shuyan Hu, Jianhua Feng, Ran Liu, Lingli Wang, Li-Rong Zheng:
Analytical models for threshold voltage, drain induced barrier lowering effect of junctionless triple-gate FinFETs. 1-4 - Pan Xue, Yilei Shen, Yang Zhao, Zhiliang Hong:
An all-digital quadrature RF transmitter with 8-bit ΣΔ modulation. 1-4 - Jiangzheng Cai, Jia Yuan, Liming Chen, Yong Hei:
A design of subthreshold SRAM cell based on RSCE and RNCE. 1-4 - Yefei Zhang, Zunchao Li, Qingzhi Meng, Yunhe Guan, Dongxu Luo:
Performance evaluation and influence of device parameters on threshold voltage of dual-material strained gate-all-around MOSFET. 1-4 - Yiou Chen, Xiang Ling, Jianhao Hu:
A dynamic and low latency wireless NoC architecture. 1-3 - Rundao Lu
A 4th-order N-path filter in 40nm CMOS with tunable Gm-C stage and reduced center-frequency offset. 1-4 - Sai Hu, Qin Wang, Zheng Guo, Jing Xie, Zhigang Mao:
Fault detection and redundancy design for TSVs in 3D ICs. 1-4 - Shyue-Kung Lu, Hao-Wei Lin, Masaki Hashizume:
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories. 1-4 - Bonan Yan, Yaojun Zhang, Enes Eken, Wujie Wen, Weisheng Zhao, Yiran Chen:
Recent progresses of STT memory design and applications. 1-4 - Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
Small-sized and noise-reducing power analyzer design for low-power IoT devices. 1-4 - Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang:
An automated test framework for SRAM-based FPGA. 1-4 - Ming Li, Haibin Yin, Peiyuan Wan:
A digitally calibrated low-power ring oscillator. 1-4 - Junli Sheng, Bingjian Jiang, Zhangwen Tang:
A high PSR SOI current-mode bandgap reference. 1-4 - Hongjiao Yang, Xiangliang Jin, Lizhen Tang, Weihui Liu, Jia Yang:
Simulation and analysis of P+/N SPAD for 3D imaging. 1-4 - Xiaoxu Kang
Humidity sensor with graphene oxide as sensing material. 1-3 - Shuaining He, Jiangyun Zhou, Jianhao Hu, Jienan Chen:
A low complexity MCMC algorithm for MIMO system with bias technique. 1-4 - Yun Liang, Shuo Wang:
Quantitative performance and power analysis of LTE using high level synthesis. 1-4 - Keita Igarashi, Masao Yanagisawa, Nozomu Togawa
Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. 1-4 - Sachin Kumar, Chip-Hong Chang
A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}. 1-4 - Shuo Li, Nan Qi, Vahid Behravan, Zhiliang Hong, Patrick Yin Chiang:
A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system. 1-4 - Shohei Shibuya, Yutaro Kobayashi, Haruo Kobayashi:
High-frequency low-distortion signal generation algorithm with arbitrary waveform generator. 1-4 - Wu Dan, Wei Li:
A programmable divider with wide division range applied in an FMCW frequency synthesizer. 1-4 - Jieqiong Cheng, Qingqing Yang, Xiaofang Zhou:
Design of a high parallelism high throughput HSPA+ Turbo decoder. 1-4 - Weiguo Zheng, Min Cai, Xiao-Yong He, Ken Xu, Zhijian Chen:
Analysis and design of quickly starting crystal oscillator. 1-4 - Yudong Li, Bo Tang, Jiang Yan:
A simulation analysis of back gate effects for FDSOI devices. 1-4 - Xiao Liang, Chuan Zhang, Shugong Xu
Coefficient adjustment matrix inversion approach and architecture for massive MIMO systems. 1-4 - Long Zhao, Chenxi Deng, Hongming Chen, Guan Wang, Yuhua Cheng:
A 1-V 23-μW 88-dB DR Sigma-Delta ADC for high-accuracy and low-power applications. 1-4 - Haozhi Ma, Zhongyi Gao, Liyang Pan, Jun Xu:
Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories. 1-4 - Yoshiki Niki, Shu Sasaki, Nobu Yamaguchi, Jian Kang, Takashi Kitahara, Haruo Kobayashi:
Flat passband gain design algorithm for 2nd-order RC polyphase filter. 1-4 - Yan-Ming Li
A novel start-up circuit for boost DC-DC converter with synchronous power-switch current-limit. 1-3 - Benqing Guo, Jun Chen, Yao Wang, Haiyan Jin, Guangjun Wen:
A 8.1 mW 0.1∼2 GHz inductorless CMOS LNTA for software-defined radio applications. 1-4 - Zhan Shi, Zhenan Tang, Fan Yang, Jiarui Wu:
Improvement of the charge pump for Maneatis PLLs. 1-3 - Lei Zhu, Qi Cheng, Jianghui Deng, Jianping Guo, Dihu Chen, Xidong Ding:
A 3.5-A buck DC-DC regulator with wire drop compensation for remote-loading applications. 1-4 - Linghan Zhang, Yunzhou Wang, Yicong Liu, Xusheng Tang:
A new intrinsic parameter extraction approach for small-signal model of AlGaN/GaN devices. 1-4 - Liang Zhu, Qian Ren, Neo Tan, Zhibo Ai:
3D resist modeling for OPC correction and verification. 1-4 - Yongsheng Wang, Hongying Wang, Fengchang Lai, Bei Cao, Yang Liu, Xiaowei Liu:
A 16-bit low-power double-sampled delta sigma modulator for audio applications. 1-4 - Ji Chen, Jen-Chung Lou, Kuan-Chang Chang, Ting-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan:
Influence of nitrogen buffering on oxygen in indium-tin-oxide capped resistive random access memory with NH3 treatment. 1-4 - Chengsen Wang, Hao Yuan, Qingwen Song, XiaoYan Tang, Renxu Jia, Yuming Zhang, Yimen Zhang, Yidong Shen:
Fabrication of 3.1kV/10A 4H-SiC Junction Barrier Schottky Diodes. 1-3 - Tianhong Ye, Kuan W. A. Chee:
Low on-resistance power MOSFET design for automotive applications. 1-4 - Jiun-Wei Horng, Tung-Hsien Chan, Toung-Yi Li:
Tunable voltage-mode four inputs universal biquad using three DVCCs. 1-4 - Cong Hao, Jianmo Ni, Hui-Tong Wang, Takeshi Yoshimura:
Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. 1-4 - Shijie Zhang, Xiaole Cui, Qiang Zhang, Yufeng Jin:
A TSV repair method for clustered faults. 1-4 - Miho Arai, Isao Shimizu, Haruo Kobayashi, Keita Kurihara, Shu Sasaki, Shohei Shibuya, Kiichi Niitsu
Finite aperture time effects in sampling circuit. 1-4 - Fangfa Fu, Jun Liao, Tao Li, Jinxiang Wang:
A deterministic optimal task migration algorithm design in NoC-based multi-core system. 1-4 - Xiaoyan Jia, Liji Wu, Beibei Wang, Xiangmin Zhang:
A novel oscillator-based TRNG for smart IC card. 1-4 - Bo Liu, Dongming Zhang, Wei-qi Ge, Yu Gong:
A novel routing structure of coarse-grained reconfigurable architecture for radar application. 1-4 - Yi Wang
Challenges and future trends for embedded security in electric vehicular communications. 1-4 - Victor Nshunguyimfura, Jie Yang, Liyuan Liu, Nanjian Wu:
An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors. 1-4 - Ke Liu, Renwei Zhang, Zhankun Du, Li Shao, Xiao Ma:
A low cost readout and processing circuit for integrated CMOS geomagnetic sensors. 1-4 - Guanyu Chen, Feng Lin, Yongliang Gao, Chunxu Li, Duowu Wen, Zhe Zhang:
The data retention improvement with 2T structure OTP on 0.18um CMOS technology. 1-4 - Kun Wang, Li Li, Feng Han, Hongbing Pan, Fan Feng, Xiao Yu:
A high performance parallel VLSI design of matrix inversion. 1-4 - Zhiyuan Li, Qingkun Li, Dianzhong Wen:
SPICE model for dual-extended memristor. 1-4 - Jiangyun Zhou, Jianhao Hu, Jienan Chen, Shuaining He:
Biased MMSE soft-output detection based on conjugate gradient in massive MIMO. 1-4 - Xian Gu, XiuJu He, Fule Li:
A calibration technique for SAR ADC based on code density test. 1-4 - Junteng Zhang, Jinhui Wang, Ligang Hou, Na Gong:
Reusable IO technique for improved utility of IC test circuit area. 1-5 - Panpan Yu, Ying Zhou, Ling Sun, Jianjun Gao:
A simple semi-analytical parameter extraction method for 40nm gatelength MOSFET. 1-4 - Tianchan Guan, Jun Han, Xiaoyang Zeng:
Exploration for energy-efficient ECC decoder of WBAN. 1-4 - Hui Shi, Zheng Sun, Yong Xu, Cheng Hu, Shan Luo, Wei Ding:
Design of the 1.0V bandgap reference on chip. 1-4 - Wei Ni, Xiaotian Wang:
Functional coverage-driven UVM-based UART IP verification. 1-4 - Junwei Li, Zibin Dai, Wei Li, Tao Chen, Yufei Zhu:
Study and implementation of cluster hierarchical memory system of multicore cryptographic processor. 1-4 - Chua-Chin Wang, Min-Yu Tseng:
10 Mbps high-voltage digital transciever on single die for 50 V voltage swing. 1-4 - Xiwei Huang, Yu Jiang, Yang Shang, Hao Yu, Lingling Sun:
A CMOS THz-sensing system towards label-free DNA sequencing. 1-4 - Yan Zhang, Qi Fang, Robert K. F. Teng, Lun Gao:
An FPGA acceleration system of exact helical CBCT image reconstruction. 1-4 - Jian Cao, Zhenxu Ye, Yuan Wang
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. 1-4 - Jianli Chen, Zheng Peng, Wenxing Zhu:
A VLSI global placement solver based on proximal alternating direction method. 1-4 - Liang Wen, Li Li, Haibo Wen, Xiaoyang Zeng:
Energy-efficient sub-threshold level shifter. 1-4 - Haibin Shao, Ke Lin, Bo Wang, Chen Chen, Fang Gao, Feng Huang, Xin'an Wang:
A high-performance charge pump with improved static and dynamic matching characteristic. 1-4 - Jinn-Yann Liu, Shi-Yu Huang, Ta-Shun Chu:
Cell-based programmable phase shifter design for pulsed radar SoC. 1-4 - Yi He, Gensheng Chen:
An inclusive fault model for Network-on-Chip. 1-4 - ZengFa Peng, Jianbin Zheng, AiLin Zhang:
A method of automatic sizing logic driver of 16nm Fin-FET. 1-5 - Nobukazu Tsukiji, Hitoshi Aoki, Masaki Kazumi, Takuya Totsuka, Masashi Higashino, Haruo Kobayashi:
A study on HCI induced gate leakage current model used for reliability simulations in 90nm n-MOSFETs. 1-4 - Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren:
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. 1-4 - Xiaoqing Wen:
Power supply noise and its reduction in at-speed scan testing. 1-4 - Yi Wang, Liji Wu, Zhi-Yuan Tu, Xiangmin Zhang, Wen Jia:
A 125KHz low frequency power recovery circuit for battery-less TPMS SoC. 1-4 - Yafei Liu, Xiangyu Li:
Low voltage adaptive delay clock buffer design. 1-4 - Ziqiang Li, Yun Chen, Xiaoyang Zeng:
OFDM synchronization implementation based on Chisel platform for 5G research. 1-4 - Huan Li, Xingbi Chen:
Deep trench junction termination employing variable-K dielectric for high voltage devices. 1-4 - Xiao Pang, Jing Wang, Chenxu Wang, Xinsheng Wang:
A DPA resistant dual rail Préchargé logic cell. 1-4 - Siliang Hua, Donghui Wang, Leiou Wang, Yan Liu, Jiarui Li:
A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. 1-4 - Ping Luo, Songlin Fu, Xiang Zhang, Yi Bao, Dongjun Wang:
An adaptive voltage scaling circuit based on dominate pole compensation. 1-4 - Guodong Zhu, Junfeng Zhang, Yang Xu, Zehong Zhang, Baoyong Chi:
A 1/2/4MHz multi-mode reconfigurable lowpass/complex bandpass CT ΣΔ modulator for short range wireless receiver. 1-4 - Xiao Wang, Zelin Shi, Baoshu Xu:
Noise analysis of a CDS circuit with offset canceling. 1-4 - Xiaoying Qiu, Leilei Miao, Runbin Shi, Zhiwei Wang, Liang Liu
A programmable baseband processor for massive MIMO uplink multi-user detection. 1-4 - Khawar Sarfraz, Mansun Chan:
Nanoscale register file circuit design - Challenges and opportunities. 1-4 - Jianing Su, Jun Han:
Design of energy efficient LDPC decoders with low-voltage strategy. 1-4 - Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren:
A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. 1-4 - Wei Zhang, Qi Chen, Ming Xia
TLP evaluation of ESD protection capability of graphene micro-ribbons for ICs. 1-4 - Xu-Guang Li, Dong Yan, Haipeng Fu, Jianguo Ma:
Survey and statistical analysis of THz detectors. 1-4 - Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li:
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. 1-4 - Fang Sun, Jin-Mei Lai:
Iterative optimization algorithm for sound localization. 1-4 - Yan Yang, Qi Wang, Yu Wang, Liyin Fu, Zongliang Huo:
A novel adaptive CMOS low-dropout regulator with 3A sink/source capability. 1-4 - Jing Deng, Xingbi Chen:
A novel SCR-LDMOS for high voltage ESD protection. 1-4 - Jinglin Huang, Qi Zhang, Li Tian, Hui Wang, Songlin Feng:
A quenching-and-reset circuit with programmable hold-off time for single photon avalanche diodes in 0.18μm CMOS. 1-4 - Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren:
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. 1-4 - Wei Xu, Wei Li:
Algorithms based on all-digital phase-locked loop for fast-locking and spur free. 1-4 - Xiangyan Xue, Xuerong Zhou, Fan Ye, Junyan Ren:
A 100MS/s 5bit fully digital flash ADC with standard cells. 1-4 - Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae:
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. 1-4 - Wenhao Xu, Xunhua Guo, Jinling Chen, Guoxing Wang:
A hall sensor microsystem for current measurement used in watt-hour meter. 1-4 - Wanghui Zou, Yun Zeng:
An analytical series resistance model for on-chip stacked inductors with inclusion of proximity effect between stacked layers. 1-4 - Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. 1-4 - James Davis, Joseph Sankman, Dongsheng Ma:
An input-powered 1.1-μA Iq 13.56 MHz RF energy harvesting system for biomedical implantable devices. 1-4 - Chulwoo Kim:
Circuit design techniques for multimedia wireline communications. 1-4 - Bingyan Liu, Yong Hei:
A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing. 1-4 - Wei Wang, Jianfeng Chen, Jia Zhou:
Droplet generating with accurate volume for EWOD digital microfluidics. 1-4 - Zunkai Huang, Yiling Ding, Li Tian, Qi Zhang, Hui Wang, Songlin Feng:
An area-efficient 10-bit two-stage DAC for active matrix organic light-emitting diodes display drivers. 1-4 - Yong Xu, Fei Zhao, Zheng Sun, Yuanliang Wu:
Design of novel chopper stabilized rail-to-rail operational amplifier. 1-4 - Yu-Kun Song, Rui Jiao, Duoli Zhang, Dongxue Gao:
Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC. 1-4 - Weikai Jiang, Hing-Mo Lam, Hui Shao, Hesheng Lin, Min Zhang
A distributive on-chip voltage regulation scheme for power supply in AMOLED driver ICs. 1-4 - Feng Huang, Ke Lin, Fang Gao, Chen Chen, Haibin Shao, Bo Wang:
A 1.2-V 7.2-μw ECG AFE with continuous time self-calibration filters. 1-4 - Xin Zhou, Ming Qiao, Yang Li, Zhaoji Li, Bo Zhang
Effect of field implantation on off- and on-state characteristics for thin layer SOI field P-channel LDMOS. 1-4 - Yann Deval
Toward 5 G: An integrated CMOS wide band arbitrary waveform generator for carrier aggregation. 1-4 - Cheng Wu, Fan Yang, Xi Tan, Chao Wang, Feng Chen, Junyu Wang:
An ECC crypto engine based on binary edwards elliptic curve for low-cost RFID tag chip. 1-4 - Yuanrui Ren, Chuan Zhang, Xing Liu, Xiaohu You:
Efficient early termination schemes for belief-propagation decoding of polar codes. 1-4 - Fa Foster Dai, Feng Zhao, Rong Jiang
Low noise coupling techniques for multi-phase oscillators. 1-4 - Akira Matsuzawa:
Automated design strategy for high performance mixed signal circuits. 1-4 - Guojun Liu:
A fully integrated 0.18 μm SiGe BiCMOS power amplifier. 1-4 - Qiangqiang Ye, Chenyu Wen, Ming Xu, Shi-Li Zhang, Dongping Wu:
Ultra-sensitive and responsive capacitive humidity sensor based on graphene oxide. 1-4 - Jicun Zhang, Nan Chen, Chuanming Liu, Libin Yao:
A low-power parallel-to-serial conversion circuit for CMOS image sensors. 1-4 - Jianfu Zhang
NBTI prediction and its induced time dependent variation. 1-4 - Jiarui Wu, Jun Yu, Jiaming Liang
Driver circuit system for temperature control of micro-hotplates: Measurement and strategy. 1-4 - Feng Ye, Haijun Wang, Ting Yi, Zhiliang Hong:
A 14-bit 2-GS/s DAC with a programmable interpolation filter. 1-4 - Hu Cao, Li Tian, Jun Liu, Hui Wang, Songlin Feng:
Color image enhancement using power-constraint histogram equalization for AMOLED. 1-4 - Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Clock skew estimate modeling for FPGA high-level synthesis and its application. 1-4 - Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Dong Yu:
An improved FFT architecture optimized for reconfigurable application specified processor. 1-4 - Jie Jin, Xuguang Zhang, Xiaoxiao Jiang, Yiyuan Fang:
Dual band power amplifier for handset application. 1-4 - Chao Yang, Shaoquan Gao, Jingjing Dong, Hanjun Jiang, Woogeun Rhee
A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications. 1-4 - Yande Jiang, Xu He, Chang Liu, Yang Guo:
An effective analytical 3D placer in monolithic 3D IC designs. 1-4 - Chong Lu, Zhikui Duan, Yi Ding, Hong-Zhou Tan
A novel clock synchronizer for low-voltage clock distribution network. 1-4 - Yu Gong, Bo Liu, Chen Mei, Rui-he Wang:
A novel configuration context cache structure of reconfigurable systems. 1-4 - Fangyuan Dang, Yuan Wang
Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. 1-4 - Nan Lyu, Ning Mei Yu, Min Yi:
An improved voltage bandgap reference with high-order curvature compensation. 1-4 - Jian Li, Jiancheng Li, Li Yang:
A nanopower, high PSRR full CMOS voltage reference circuit consisting of subthreshold MOSFETs. 1-4 - Sun Qiang:
A peak power optimization scheduling algorithm for single cycle operations and multi-cycle operations. 1-4 - Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang:
Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure. 1-4 - Liyin Fu, Yu Wang, Qi Wang, Shiyang Yang, Yan Yang, Zongliang Huo:
A high efficiency all-PMOS charge pump for 3D NAND flash memory. 1-4 - Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren:
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. 1-4 - Baoyong Chi, Lixue Kuang, Haikun Jia, Zhiping Wang, Zhihua Wang:
A 60-GHz wireless transceiver with dual-mode power amplifier for IEEE 802.11ad in 65nm CMOS. 1-4 - Longcheng Que, Jian Lv, Simon S. Ang:
Design of a high voltage gate driver module. 1-4 - YanHeng Lu, Wei Cheng, Leilei Huang, Xiaoyang Zeng, Yibo Fan:
A flexible HEVC intra mode decision hardware for 8kx4k real time encoder. 1-4 - Chaochao Feng, Zhuofan Liao, Zhonghai Lu, Axel Jantsch
Performance analysis of on-chip bufferless router with multi-ejection ports. 1-4 - Xiangliang Jin, Feng Zhang:
System-level modeling and analysis of third order MEMS accelerometer. 1-4 - Wang Qian, Wang Pengjun, Gong Daohui:
Design of explicit-pulse generators with CNTFET. 1-4 - Abdel Martinez Alonso
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. 1-4 - Ning Li, Ke Lin, Shanshan Yong, Xiaofei Chen, Xinan Wang, Xing Zhang:
Design and implementation of a MAC protocol for a wearable monitoring system on human body. 1-4 - Shaowei Zhen, Ji Wang, Dongjie Yang, Canhua Cao, Ping Luo:
A load-transient-enhanced output-capacitor-free low-dropout regulator based on an ultra-fast push-pull amplifier. 1-4 - Litong Nie, Zhigong Wang, Lu Tang, Junliang Wang, Luosi Gao:
A CMOS charge pump with dual compensation amplifiers for phase-locked loops synthesizer. 1-4 - Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng:
A configurable SoC design for information security. 1-4 - Guangfa Si, Yong-Sheng Yin, Honghui Deng:
Design of a novel high-accuracy LED driving chip. 1-4 - Jinglei Huang, Zhigang Li, Wei Zhong, Song Chen
Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips. 1-4 - An Chen:
Hardware security applications of emerging nonvolatile memories. 1-4 - Yujia Wang, Jiajia Chen:
New design for low complexity and low power partial programmable shifters. 1-4 - Li Wang, Rui Ma, Fei Lu, Albert Z. Wang, Zongyu Dong, Xin Wang, Chen Zhang, Bin Zhao, Siqiang Fan, He Tang:
Function-based ESD protection circuit design verification for BGA pad-ring array. 1-4 - Liwei Yang, Yao Chen
System-level design solutions: Enabling the IoT explosion. 1-4 - Chih-Hung Chen, Xuesong Chen, D. Y. Wu, Chao Sheng Chen:
Future low-noise technologies for RF, analog and mixed-signal integrated circuits. 1-4 - Xiaofei Chen, Xiaorui Liu, Yingjie Zhang, Xuecheng Zou, Shuangxi Lin:
An overview of soft-switching technique for flyback converters. 1-4 - Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. 1-4 - Feng Ma, Xin-Wang Zhang, Baoyong Chi:
A 100M-1.5 GHz harmonic-rejection SDR receiver front-end. 1-4 - Jienan Chen, Jianhao Hu, Jiangyun Zhou:
Ultra-short length stochastic computation based on multiple partition computing. 1-4 - Bukun Pan, Jing Jin, Jianjun Zhou:
A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability. 1-4 - Meilin Wan, Zhenzhen Zhang, Kui Dai, Xuecheng Zou:
A 1-V 2.5-ppm/°C second-order compensated bandgap reference. 1-4 - Yasunori Kobori, Taifeng Wang, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi:
EMI reduction by analog noise spread spectrum in new ripple controlled converter. 1-4 - Bei Cao, Zhiyuan Li, Dianzhong Wen:
Generation of low power testing based on novel SIC sequences. 1-4 - Haibin Yin, Xiaohong Peng, Peiyuan Wan, Jinhui Wang, Ligang Hou:
Design and testing of CMOS compatible EEPROM. 1-4 - Shinnosuke Yoshida, Youhua Shi
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. 1-4 - Xiang Zhongyuan, Zhang Feng:
A dynamic reprogramming scheme to enhance the reliability of RRAM. 1-4 - Yuejun Zhang, Pengjun Wang, Gang Li, Haoyu Qian, Xiaomin Zheng:
Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOS. 1-4 - Chaojiang Li, Xiaoxia Wang, Vibhor Jain, Hanyi Ding, Myra Boenke, Dawn Wang, Randy Wolf, Alvin J. Joseph:
2.4/5.5GHz LNA switch designs based on high resistive substrate 0.35um SiGe BiCMOS. 1-4 - Jiaxing Wei, Jianfeng Wang, Ning Wang, Siyang Liu, Weifeng Sun:
A novel stack package solution of AC-DC chip for high-power density adapters. 1-4 - Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng:
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. 1-4 - Steven H. Voldman:
Electrical Overstress (EOS): Challenges for component and system-level co-design. 1-4 - Long Zhao, Ji He, Yuhua Cheng:
A 6bit 4GS/s current-steering digital-to-analog converter in 40nm CMOS with adjustable bias and DfT block. 1-4 - Meng-Chou Chang, Kai-Lun He:
Design of low-power FinFET-based TCAMs with unevenly-segmented matchlines for routing table applications. 1-4 - Jiachen Hao, Zheng Song, Baoyong Chi:
A reconfigurable analog baseband for low-power Wi-Fi receiver. 1-4 - Jianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin:
A low cost and high reliability true random number generator based on resistive random access memory. 1-4 - Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng:
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. 1-4 - Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren:
An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. 1-4 - Yuanpei Gao, Haijiang Ye, Jian Wang, Jinmei Lai:
FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique. 1-4 - Dongsheng Liu, Weila Lei, Yin Liu, Lun Li:
Energy-efficient and area-efficient switching scheme for SAR ADCs. 1-4 - Ting Liu, Kuan W. A. Chee:
Modeling and design of the LDMOSFET for RF power amplifier applications. 1-4 - Zezhong Yang, Jinhui Wang, Ligang Hou, Na Gong:
Novel CMOS technology compatible nonvolatile on-chip hybrid memory. 1-4 - Tao Zhang, Jiyao Zhang:
Design and implementation of light load energy saving current-limiting circuit. 1-4 - Shujuan Yin:
The compact Vth model for biaxial strained Si NMOSFET. 1-4 - Goro Suzuki:
Waveform base clock tree delay analysis using parallel processing. 1-5 - Kaihua Cao, Heng Zhao, Mengxing Wang, Weisheng Zhao:
Spin orbit torques for ultra-low power computing. 1-4 - Chunhui Li, Lei Ma, Junhui Xiang, Hao Min:
An asynchronous delay line TDC for ADPLL in 0.13um CMOS. 1-4 - Jianqiao Tang, Runxi Zhang, Chunqi Shi:
A wideband VCO with constant tuning-gain and uniform sub-band interval for single-chip UHF RFID reader. 1-4 - Xinpeng Xing, Gaozhan Cai, Georges G. E. Gielen
A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radio. 1-4 - Yuang Zhang, Li Li, Axel Jantsch
Exploring stacked main memory architecture for 3D GPGPUs. 1-4 - Xiaojin Fu, He Tang:
A novel power optimization mechanism for pipelined ADCs. 1-4 - Huixian Ye, Li Tian, Qi Zhang, Hui Wang, Songlin Feng:
CMOS image sensor with programmable compressed sensing. 1-4 - Masato Tamura, Atsushi Ito, Makoto Ikeda:
Optimal design on asynchronous system with gate-level pipelining. 1-4 - Lianxi Liu, Wei Tu, Junchao Mu, Zhangming Zhu, Yintang Yang:
A voltage doubling AC-DC converter with offset-controlled comparators for piezoelectric energy harvester. 1-4 - Mengnan Wu, Yang Yang, Liangliang Dai, Xinxin Zhang, Hongbin Sun, Ruizhi Zhang, Jianxiao Wang, Nanning Zheng:
An experimental study on the potential use of ReRAM as SSD buffer. 1-4 - Xiang Jiang, Jun Cheng, Liang Li, Ting Zhang, Liao Gong, Qiyun Ma:
Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter. 1-4 - Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
An energy-efficient microprocessor using multilevel error correction for timing error tolerance. 1-4 - Kenichi Okada
A 28-Gb/s 60-GHz wireless transceiver in 65nm CMOS with 64QAM capability. 1-4 - Wei Ni, Jichun Zhang:
Research of reusability based on UVM verification. 1-4 - Yadi Guo, Renyuan Chang, Jun Fu, Baoyong Chi, Yudong Wang:
Analysis and design of a high linearity quadrature demodulator based on SiGe BiCMOS process. 1-4 - Shudong Tian, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
Motion artifact removal based on ICA for ambulatory ECG monitoring. 1-4 - Yoshiki Sugawara, Nobukazu Takai, Masato Kato, Hiroaki Seki, Kento Suzuki, Haruo Kobayashi:
Automatic design of doubly-terminated RC polyphase filters by using distributed genetic algorithm. 1-4 - Jiyu Chen, Song Jia, Yuan Wang:
A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. 1-4 - Xiangliang Jin, Zhenyu Jiang, Manfang Tian:
TCAD simulations of novel Interrupted-P-Finger UV/Blue photodiode based on CMOS process. 1-4 - Qin Chen, Dongpo Chen, Tingting Mo:
A SFA and I/Q mismatch auto-calibration scheme for high IRR multi-mode GPS RF receiver. 1-4 - Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang:
A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC. 1-4 - Feng Zhang, Hao Ju, Chengying Chen:
A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0. 1-4 - Jiangping He, Jiang Sun, Bo Zhang
A wide range PWM signal frequency converter with the identical duty cycle. 1-4 - Jiayi Hu, Qin Wang, Jianfei Jiang, Jing Xie, Zhigang Mao:
A crosstalk avoidance scheme based on re-layout of signal TSV. 1-4 - Jiang Bingjian, Junli Sheng, Zhangwen Tang:
PDK design of 0.13um SOI process. 1-4 - Zheng Zheng, Xin'an Wang, Zhaoyang Guo, Guoxing Zhang:
An automatic software/hardware verification platform prototype for reconfigurable audio algorithm in media SoC. 1-4 - You Yin, Sumio Hosaka:
Nanosecond-order fast switching and ultra-multilevel storage in lateral GeTe and Ge1Sb4Te7-based phase-change memories. 1-4 - Ken Xu, Min Cai, Xiao-Yong He, Zhijian Chen, Weiguo Zheng:
An automatic DC-Offset cancellation method and circuit for RF transceivers. 1-4 - Shu-Hang Zhang, Yu-Cheng Feng, Miin-Shyue Shiau, Qi-Ming Wan, Don-Gey Liu:
A high-slew rate rail-to-rail operational amplifier by flipped voltage followers. 1-4 - Hung-Kai Chen, Wei-Zen Chen, Zhiyuan Ren
A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter. 1-4 - Yubin Zhang, Yajie Qin, Han Jin:
A high input impendence AC-coupled SoC suitable for wearable ExG monitor. 1-4 - Feng Ru, Xiaohong Peng, Ligang Hou, Jinhui Wang, Shuqin Geng, Chen Song:
The design of face recognition system based on ARM9 embedded platform. 1-4 - Xinsheng Wang, Lifeng Shang, Heyi Yin:
Reliability concerns on time-to-digital converter due to bias temperature instability in nanometer era. 1-4 - Xingye Zhou, Zhihong Feng, Yuanjie Lv, Xin Tan, Yuangang Wang, Guodong Gu, Xubo Song, Peng Xu, Shaobo Dun, Shujun Cai:
Dependency of current collapse on the device structure of GaN-based HEMTs. 1-4 - Xiao Wang, Dongyue Jin, Wanrong Zhang, Xinyi Zhao, Yanling Guo, Qiang Fu:
Novel superjunction collector design of power SiGe HBTs for high fT×BVCEO×β product. 1-4 - Zhongxing Zhang, Jie Yang, Honglong Li, Liyuan Liu, Jian Liu, Nanjian Wu:
High-speed object detection based on a hierarchical parallel vision chip. 1-4 - Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. 1-4 - Wei Zhao, Ligang Hou, Xiaohong Peng, Jinhui Wang, Jingyan Fu, Yang Yang:
A TSV alignment design for multilayer 3D IC. 1-4 - Quan Sun, Min Qi, Yi Gu, Liang Tang, Donghai Qiao:
A 10-bit DAC with 2.9 μν low frequency noise for high performance MEMS capacitive accelerometer application. 1-4 - Chee Wee Liu
Advanced germanium channel transistors (invited). 1-4 - Makoto Ikeda:
Design and optimization of asynchronous circuits with gate-level pipelining. 1-4 - Zhou Chuang Wang, Zi Bin Dai:
High-speed realization of trivium based on multi-core cryptographic processor. 1-4 - Jiaan Dai, Xiaofang Zhou, Linshan Zhang, Gerald E. Sobelman:
Network-coding-based distributed relay scheme for PLC networks. 1-4 - Tony T. Kim, Jun Zhou, Yong Lian
Opportunities and challenges: Ultra-low voltage digital IC design techniques. 1-4 - Sung Hyun Jo, Hagop Nazarian:
Resistive random access memory with high selectivity and ON/OFF ratio amplification sensing. 1-3 - Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye
LVDS transmitter with optimized high power-efficiency 8: 1 MUX. 1-4 - Zhicheng Xie, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
A low-cost SoC implementation of AES algorithm for bio-signals. 1-4 - Xiaodong Deng, Yihu Li, Wen Wu, Yong-Zhong Xiong:
D-band down conversion chipset with I-Q outputs using 0.13μm SiGe BiCMOS technology. 1-4 - Mengyin Jiang, Yuan Wang
A reference-less all-digital burst-mode CDR with embedded TDC. 1-4 - Weijiang Wang, Yingtao Ding, Shan Cao, Xianli Zhao:
Design of a dynamically reconfigurable arithmetic unit for matrix algorithms. 1-4 - Kim Batselier
An adaptive dynamical low-rank tensor approximation scheme for fast circuit simulation. 1-4 - Haoyu Mei, Wei Li:
A low power 1.5GHz Gm-C filter with 0-40dB variable gain in 65-nm CMOS technology. 1-4 - Fengshuo Tian, Weiguang Sheng, Weifeng He:
An automatic translation and parallelization system for general purpose reconfigurable processor. 1-4 - Teng Chen, Leli Peng, Haibin Li, Ning Ding, Cheng Ma, Yuchun Chang:
A 2-V 40-MS/s 14-bit pipelined ADC for CMOS image sensor. 1-4 - Yuqing Hu, Lijun Zhang, Youzhong Li, Qixiao Zhang, Erliang Li, Wei Jiang:
Design and implementation of precise measuring method for the access time of embedded memory. 1-4 - Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee:
Distinguishing dynamic bridging faults and transition delay faults. 1-4 - Guoqiang Hang, Guoquan Zhu:
A new Schmitt trigger with adjustable hysteresis using floating-gate MOS threshold inverter. 1-4 - Yasunori Kobori, Takuya Arafune, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi:
Selectable notch frequencies of EMI spread spectrum using pulse modulation in switching converter. 1-4 - Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui:
A countermeasure for power analysis to scalar multiplication of ECC hardware. 1-4 - Hupo Wei, Xiaole Cui, Qiang Zhang, Yufeng Jin:
An enhanced decoder for multiple-bit error correcting BCH codes. 1-4 - Nan Han, Yuan Wang
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. 1-4 - He Wang, Xi Tan, Feng Chen, Chao Wang, Junyu Wang:
A Viterbi decoder for UHF RFID digital baseband. 1-4 - Masahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar, Takahiro Miki, Osamu Kobayashi:
Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniques. 1-4 - Wei Ni, Zhenwei Liu:
A routing algorithm for Network-on-Chip with self-similar traffic. 1-4 - Zhijian Chen, Min Cai, Ken Xu, Weiguo Zheng:
A 2.4GHz low noise high linearity RF front-end design. 1-4 - Shuqin Zhang, Chunsheng Jiang, Libin Liu, Jing Wang, Jun Xu:
Investigation of line tunnel field effect transistor with Ge/Si heterojunction. 1-4 - Yongquan Li, Mei Jiang, Liangwei Cai:
A 30 nA, 6.6 ppm/°C, high PSRR subthreshold CMOS voltage reference. 1-4 - Fang Gao, Jipan Huang, Hongying Chen, Xin'an Wang:
Development of TFET 0.13 μm standard cell library for ultra-low power applications. 1-4 - Li Yang, Jiancheng Li, Minghua Tang, Lei Cai, Jian Li, Miaoxia Zheng:
A high-sensitivity ASK demodulator for passive UHF RFID tags with automatic voltage limitation and average voltage detection. 1-4 - Zhang Jie, Jin Lin:
An iterative synthesis method for timing-driven design. 1-3 - Zhenzhen Tian, Rendong Ying, Peilin Liu, Guoxing Wang, Yong Lian
Event-driven analog-to-digital converter for ultra low power wearable wireless biomedical sensors. 1-4 - Lian Huai, Samer L. Hijazi, Raúl A. Casas, Gerald E. Sobelman:
A low complexity algorithm and architecture for MIMO detection without QR decomposition. 1-4 - Zehua Chen, Weiyin Wang, Hei Wong
Low-voltage CMOS DC-DC converters for energy harvesting applications. 1-4 - Bingqiang Jing, Xiaole Cui, Yalin Ran, Yufeng Jin:
Post-bond test for TSVs using voltage division. 1-4 - Qian Liang, Jinhui Wang, Peiyuan Wan, Ligang Hou, Na Gong:
DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processor. 1-4 - Zheng Sun, Wei Ding, Yong Xu, Ying Huang, Guangyan Ma, Yuanliang Wu:
Self-recovering short-circuit protection circuit for RF class-D power amplifier. 1-4 - Yao Peng, Yanfei Yang, Xiaofei Qi:
High performance protocol converters for two phase quasi-delay insensitive system-level communication. 1-4 - Yuanlong Xiao, Jian Wang, Jinmei Lai:
A power efficient current-mode differential driver for FPGAs. 1-4 - Honglong Li, Zhongxing Zhang, Jie Yang, Liyuan Liu, Nanjian Wu:
A novel vision chip architecture for image recognition based on convolutional neural network. 1-4 - Shuo Huang, Xuan Li, Xiaoyong Li:
A 14b 1GS/s DAC with SFDR > 80 dBc across the whole nyquist band by mixed total 3-dimesional sort-and-combine and dynamic element matching. 1-4 - Yuxiang Fu, Li Li, Yuang Zhang, Hongbing Pan, Feng Han, Kun Wang:
Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links. 1-4 - Kaining Han, Jianhao Hu, Jienan Chen, Sheng Yang:
A high performance massive MIMO detector based on log-domain belief-propagation. 1-4 - Wen-Cheng Lai
A 10-bit 40 MS/s successive approximation register analog-to-digital converter with Vcm-based method for wireless communications. 1-5 - Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. 1-4 - Yunzhong Zhu, Tao Li, Jingpeng Guo, Haiyang Zhou, Fangfa Fu:
A novel low-cost interface design for SystemC and SystemVerilog Co-simulation. 1-4 - Takuya Arafune, Yutaro Kobayashi, Shohei Shibuya, Haruo Kobayashi:
Fibonacci sequence weighted SAR ADC algorithm and its DAC topology. 1-4 - Ching-Ting Lee, Jhe-Hao Chang, Chun-Yen Tseng:
Photoelectrochemically recessed AlGaN/GaN monolithic inverter incorporating LiNbO3 ferroelectric film. 1-4 - Wen-Quan He, Yu-Chun Lin, Jui-Yi Hung, Shyh-Jye Jou:
Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead. 1-4 - Cong Li, Jiancheng Li, Wenxiao Li, Shunqiang Xu, Yaling Chen:
A new reading scheme for multitime programmable (MTP) memory cells. 1-4 - Masashi Higashino, Hitoshi Aoki, Nobukazu Tsukiji, Masaki Kazumi, Takuya Totsuka, Haruo Kobayashi:
Study on maximum electric field modeling used for HCI induced degradation characteristic of LDMOS transistors. 1-4 - Xiaofei Chen, Bo Wang, Ke Lin, Ning Li, Chen Chen, Haibin Shao, Xin'an Wang:
Design and implementation of a body monitoring baseband system for human body communication. 1-4 - Bin Wan, Cindy Zhang, Xingang Wang:
Multi-technology simulation with mixed design environments. 1-4 - Wei Xu, Runxi Zhang, Chunqi Shi:
Research of segmented 8bit voltage-mode R-2R ladder DAC. 1-4 - Lei Chao, Zhi Zeng, Kaidi Zhang, Wei Wang, Jia Zhou:
Application of cellulose triacetate as biocompatible/biodegradable dielectrics in EWOD devices. 1-4 - Chenxi Deng, Long Zhao, Hui Zheng, Yuhua Cheng:
A 1.8-V 12-bit self-calibrating SAR ADC with a novel comparator. 1-4 - Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren:
A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. 1-4 - Wenchao Zhang, Song Chen
A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. 1-4 - Hong-Fan Huang, Xiaoyong Liu, Jin-Shan Shi, Lin-Qing Zhang, Sheng-Xun Zhao, Min-Zhi Lin, Bin Wu, Peng-Fei Wang:
Investigation of a GaN-on-Si HEMT optimized for the 5th-generation wireless communication. 1-4 - Xuerong Zhou, Xiangyan Xue, Fan Ye, Junyan Ren:
I/Q imbalance estimation in OFDM systems. 1-4 - Yanqin Chen, Hongguang Zhang, Xu Guo, Zhiliang Hong:
A 400mV supply voltage self-start clock generator for energy harvest system. 1-3 - Guanghua Wu, Hong Chen, Yanyi Meng, Xitian Long, Kun Yang, Xueping Jiang:
A novel symbol synchronization algorithm and low-complexity circuits design for zero-IF GFSK demodulator. 1-4 - Kento Suzuki, Nobukazu Takai, Masato Kato, Hiroaki Seki, Yoshiki Sugawara, Haruo Kobayashi:
Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimization. 1-4 - Chao Peng, Jinyong Zhang, Xu Zhang, Lei Wang:
A 16-channel electrode driver with precise calibration for electrical neural stimulation. 1-4 - Song Jia, Weiting Li, Wenyi Tang, Yuan Wang
A low power and high speed CAM design using pulsed voltage for search-line. 1-4 - Suoping Hu, Dongpo Chen, Tingting Mo:
A dual-band frequency tunable complex filter with stable quality-factor in different temperatures. 1-4 - Chen Zou, Weikang Qian, Jie Han:
DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis. 1-4 - Bowen Yang, Zhijian Lu, Jianjun Zhou:
A 6-13 GHz wide-tuning-range low-phase-noise ring oscillator utilizing frequency multiplication technique. 1-4 - Xusong Liu, Lei Ma, Junhui Xiang, Na Yan, Haolv Xie, Xiaowei Cai:
A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS. 1-4 - HaiJun Lin, Xiao Yang:
Split-based 200Msps and 12 bit ADC design. 1-4 - RongRong Zhou, Fen Ge, Gui Feng, Ning Wu:
A network components insertion method for 3D application-specific Network-on-Chip. 1-4 - Long Zhao, Chenxi Deng, Yuhua Cheng:
A 6b 2b/cycle SAR ADC beyond 1GS/s with hybrid DAC structure and low kickback noise comparators. 1-4 - Ligang Hou, Jingsong Zhi, Lin Zhu, Jinhui Wang, Xiaohong Peng, Shuqin Geng:
A fast vector reuse verification method for standard cell library. 1-4 - Saki Tajima, Youhua Shi
A low-power soft error tolerant latch scheme. 1-4 - Tian Zou, Zuying Luo:
PS-BloTAM: Pre-sampling based architecture-level temperature analysis methodology. 1-4 - Liang Liu
Circuits and systems for 5G network: Massive MIMO and advanced coding. 1-4 - Yoshiki Sunaga, Naoya Shiraishi, Koyo Asaishi, Nobukazu Tsukiji, Yasunori Kobori, Nobukazu Takai, Haruo Kobayashi:
High efficiency single-inductor dual-output DC-DC converter with ZVS-PWM control. 1-4 - Zhixiong Di, Yanlong Wang, Shuang Qiao, Qianyin Xiang
LC-KO: A congestion-aware and area&timing-oriented placement method. 1-4 - Jianmo Ni, Cong Hao, Nan Wang, Qian Ai, Takeshi Yoshimura:
Primal-dual method based simultaneous functional unit and register binding. 1-4 - Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A timing failure tolerance design with in-field simultaneous error detection and correction. 1-4 - Jiangping He, Pengfei Liao, Bo Zhang
A high reliability synchronous boost converter with spike suppression circuit. 1-4 - C. Qian, Mao-Lin Shi, Lin Chen, Qing-Qing Sun, Peng Zhou, S. J. Ding, D. W. Zhang:
Investigation of self-heating effect in SOI tunnel field-effect transistor. 1-4 - Jun Chen, Benqing Guo, Boyang Zhang, Guangjun Wen:
A 0.06 mm2 6 dBm IB1db wideband CMOS class-AB LNTA for SAW-less applications. 1-4 - Leilei Huang, Wei Cheng, Xiaoyang Zeng, Yibo Fan:
A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders. 1-4 - Yangjie Zhang, Wei Cao, Lingli Wang:
Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA. 1-4
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