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ASP-DAC 2009: Yokohama, Japan
- Kazutoshi Wakabayashi:
Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009. IEEE 2009, ISBN 978-1-4244-2748-2 - Mitsuo Saito:
Challenges to EDA system from the view point of processor design and technology drivers. - Wolfgang Rosenstiel:
Automated synthesis and verification of embedded systems: wishful thinking or reality? - Leon Stok:
From restrictive to prescriptive design.
On-chip communication architectures
- Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang:
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. 1-6 - Yue Qian, Zhonghai Lu, Wenhua Dou:
Analysis of communication delay bounds for network on chips. 7-12 - Ping Zhou
, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang, Li Zhao:
Frequent value compression in packet-based NoC architectures. 13-18 - Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang:
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. 19-24 - Sudeep Pasricha, Nikil D. Dutt
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. 25-30
Dealing with thermal issues
- Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee:
Stochastic thermal simulation considering spatial correlated within-die process variations. 31-36 - Francesco Zanini, David Atienza, Giovanni De Micheli:
A control theory approach for thermal balancing of MPSoC. 37-42 - Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim
Thermal optimization in multi-granularity multi-core floorplanning. 43-48 - Yu-Wei Yang, Katherine Shu-Min Li:
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement. 49-54 - Shih-An Yu, Pei-Yu Huang, Yu-Min Lee:
A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects. 55-60
Advances in behavioral synthesis
- Gregory Lucas, Scott Cromar, Deming Chen:
FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. 61-66 - Chia-I Chen, Juinn-Dar Huang:
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. 67-72 - Yibo Chen, Yuan Xie:
Tolerating process variations in high-level synthesis using transparent latches. 73-78 - Feng Wang, Yuan Xie, Andrés Takach:
Variation-aware resource sharing and binding in behavioral synthesis. 79-84 - Junbo Yu, Qiang Zhou, Jinian Bian:
Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. 85-90
University LSI design contest
- Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda:
A wireless real-time on-chip bus trace system. 91-92 - Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo:
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. 93-94 - Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. 95-96 - Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. 97-98 - Ahmet Öncü
Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio. 99-100 - Hui Shao, Chi-Ying Tsui
An inductor-less MPPT design for light energy harvesting systems. 101-102 - Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda:
A 1 GHz CMOS comparator with dynamic offset control technique. 103-104 - Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada:
Circuit design using stripe-shaped PMELA TFTs on glass. 105-106 - Hui Shao, Chi-Ying Tsui
Low energy level converter design for sub-Vth logics. 107-108 - Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai, Masao Hotta:
A Time-to-Digital Converter with small circuitry. 109-110 - H. Oshiyama, Toshihiro Matsuda, K. Suzuki, Hideyuki Iwata, Takashi Ohzone:
A VDD independent temperature sensor circuit with scaled CMOS process. 111-112 - Chihiro Kawabata, Yasuhiro Sugimoto:
A current-mode DC-DC converter using a quadratic slope compensation scheme. 113-114 - Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu:
Ultra low-power ANSI S1.11 filter bank for digital hearing aids. 115-116 - Daisaku Seto, Minoru Watanabe:
An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. 117-118 - Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A low-power FPGA based on autonomous fine-grain power-gating. 119-120 - Xin-Yu Shih
A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. 121-122 - Ming-Chien Tsai, Ching-Hwa Cheng:
A full-synthesizable high-precision built-in delay time measurement circuit. 123-124 - Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip. 125-126 - Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto:
A high performance LDPC decoder for IEEE802.11n standard. 127-128 - Masa-Aki Fukase, Kazunori Noda, Atsuko Yokoyama, Tomoaki Sato:
Design and chip implementation of the ubiquitous processor HCgorilla. 129-130 - Liang-Bi Chen
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. 131-132 - Dan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu:
A multi-task-oriented security processing architecture with powerful extensibility. 133-134 - Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong:
A delay-optimized universal FPGA routing architecture. 135-136
MPSoC and IP integration
- HaNeul Chon, Taewhan Kim:
Timing variation-aware task scheduling and binding for MPSoC. 137-142 - Katalin Popovici, Ahmed Amine Jerraya:
Flexible and abstract communication and interconnect modeling for MPSoC. 143-148 - Eric Cheung, Harry Hsieh, Felice Balarin:
Partial order method for timed simulation of system-level MPSoC designs. 149-154 - Zhenxin Sun, Weng-Fai Wong
A UML-based approach for heterogeneous IP integration. 155-160
Power analysis and optimization
- Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. 161-166 - Jason Cong, Puneet Gupta
On the futility of statistical power optimization. 167-172 - Shih-Hsu Huang, Chun-Hua Cheng:
Timing driven power gating in high-level synthesis. 173-178 - Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. 179-184 - Yiyu Shi, Wei Yao, Jinjun Xiong
Incremental and on-demand random walk for iterative power distribution network analysis. 185-190
Logic and arithmetic optimization
- Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang:
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. 191-196 - F. S. Chim, T. K. Lam, Y. L. Wu:
On improved scheme for digital circuit rewiring and application on further improving FPGA technology mapping. 197-202 - Amit Verma, Ajay Kumar Verma, Philip Brisk
Hybrid LZA: a near optimal implementation of the leading zero anticipator. 203-209 - Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. 210-215
EDA acceleration using new architectures
- Reiji Suda, Takayuki Aoki, Shoichi Hirasawa, Akira Nukada, Hiroki Honda, Satoshi Matsuoka:
Aspects of GPU for general purpose high performance computing. 216-223 - Damir A. Jamsek:
Designing and optimizing compute kernels on NVIDIA GPUs. 224-229 - Masato Edahiro:
Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration. 230-233
System-level design of 3D chips and configurable systems
- Xiangyu Dong, Yuan Xie:
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). 234-241 - Srinivasan Murali, Ciprian Seiculescu, Luca Benini
Synthesis of networks on chips for 3D systems on chips. 242-247 - Fabio Cancare, Marco D. Santambrogio
An application-centered design flow for self reconfigurable systems implementation. 248-253 - Concepción Sanz, Manuel Prieto
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories. 254-259
Advances in timing analysis and modeling
- Kanupriya Gulati, Sunil P. Khatri:
Accelerating statistical static timing analysis using graphics processing units. 260-265 - Hiroshi Fuketa, Masanori Hashimoto
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. 266-271 - Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng:
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. 272-277 - Lin Xie, Azadeh Davoodi:
Bound-based identification of timing-violating paths under variability. 278-283 - Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Adaptive techniques for overcoming performance degradation due to aging in digital circuits. 284-289
Hardware dependent software for multi- and many-core embedded systems
- Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller:
Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. 290-292 - Wolfgang Ecker, Stefan Heinen, Michael Velten:
Using a dataflow abstracted virtual prototype for HdS-design. 293-300 - Yasutaka Tsunakawa:
Needs and trends in embedded software development for consumer electronics. 301-303 - Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski:
Hardware-dependent software synthesis for many-core embedded systems. 304-310
System level architectures
- Cathy Qun Xu, Chun Jason Xue
Computation and data transfer co-scheduling for interconnection bus minimization. 311-316 - Antonino Tumeo
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. 317-322 - Gianluca Palermo
Variability-aware robust design space exploration of chip multiprocessor architectures. 323-328 - Young-Su Kwon, Bontae Koo, Nak-Woong Eum:
Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor. 329-334 - Andhi Janapsatya, Sri Parameswaran
HitME: low power Hit MEmory buffer for embedded systems. 335-340
Beyond traditional floorplanning and placement
- Cheng-Yu Wang, Wai-Kei Mak:
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. 341-346 - Xin Li, Yuchun Ma, Xianlong Hong:
A novel thermal optimization flow using incremental floorplanning for 3D ICs. 347-352 - Linfu Xiao, Evangeline F. Y. Young:
Analog placement with common centroid and 1-D symmetry constraints. 353-360 - Jason Cong, Guojie Luo:
A multilevel analytical placement for 3D ICs. 361-366 - Jia Wang, Hai Zhou:
Exploring adjacency in floorplanning. 367-372
Signal/power integrity and simulation
- Yiyu Shi, Jinjun Xiong
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. 373-378 - Hai Wang, Hao Yu, Sheldon X.-D. Tan:
Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. 379-384 - Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto
High performance on-chip differential signaling using passive compensation for global communication. 385-390 - Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng:
Noise minimization during power-up stage for a multi-domain power network. 391-396 - He Peng, Chung-Kuan Cheng:
Parallel transistor level circuit simulation using domain decomposition methods. 397-402 - Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry:
Fast circuit simulation on graphics processing units. 403-408
Challenges in 3D integrated circuit design
- Mitsumasa Koyanagi, Takafumi Fukushima
Three-dimensional integration technology and integrated systems. 409-415 - Nobuaki Miyakawa:
A 3D prototyping chip based on a wafer-level stacking technology. 416-420 - David S. Kung, Ruchir Puri:
CAD challenges for 3D ICs. 421-422 - Sachin S. Sapatnekar
Addressing thermal and power delivery bottlenecks in 3D circuits. 423-428 - Charles C. Chiang, Subarna Sinha:
The road to 3D EDA tool readiness. 429-436
Energy-aware system level design methodology
- Florin Balasa, Ilie I. Luican, Hongwei Zhu, Doru V. Nasui:
System-level exploration tool for energy-aware memory management in the design of multidimensional signal processing systems. 443-448 - Ittetsu Taniguchi
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. 449-454 - Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang
A framework for estimating NBTI degradation of microarchitectural components. 455-460
Design for manufacturing and reliability
- Rajesh Garg, Sunil P. Khatri:
Efficient analytical determination of the SEU-induced pulse shape. 461-467 - Cheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee:
Post-routing redundant via insertion with wire spreading capability. 468-473 - Lerong Cheng, Puneet Gupta
Accounting for non-linear dependence using function driven component analysis. 474-479 - Jia Wang, Hai Zhou:
Risk aversion min-period retiming under process variations. 480-485 - Kwangok Jeong, Andrew B. Kahng:
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. 486-491 - Lide Zhang, Robert P. Dick:
Scheduled voltage scaling for increasing lifetime in the presence of NBTI. 492-497
Analog, RF and mixed-signal CAD
- Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya:
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. 498-503 - Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao
Automated design and optimization of circuits in emerging technologies. 504-509 - Samiran DasGupta, Pradip Mandal:
An automated design approach for CMOS LDO regulators. 510-515 - Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu:
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. 516-521 - Prateek Bhansali, Jaijeet S. Roychowdhury:
Gen-Adler: the Generalized Adler's equation for injection locking analysis in oscillators. 522-527
Designers' forum: consumer SoC
- Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori:
Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture. 528-534 - Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka:
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. 535-539 - Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji Horii, Hisato Yoshida:
UniPhier: series development and SoC management. 540-545
System level simulation and modeling
- Aimen Bouchhima, Patrice Gerin, Frédéric Pétrot:
Automatic instrumentation of embedded software for high level hardware/software co-simulation. 546-551 - Eric Cheung, Harry Hsieh, Felice Balarin:
Fast and accurate performance simulation of embedded software for MPSoC. 552-557 - Chen Kang Lo, Ren-Song Tsay:
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. 558-563 - Farhad Mehdipour, Hamid Noori
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. 564-569
Chip and package routing techniques
- Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. 570-575 - Yue Xu, Yanheng Zhang, Chris Chu:
FastRoute 4.0: global router with efficient via minimization. 576-581 - Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang
High-performance global routing with fast overflow reduction. 582-587 - Jin-Tai Yan, Zhi-Wei Chen:
IO connection assignment and RDL routing for flip-chip designs. 588-593 - Lijuan Luo, Martin D. F. Wong
On using SAT to ordered escape problems. 594-599 - Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound. 600-605
Compilation techniques for embedded systems
- Wen-Wen Hsieh, TingTing Hwang:
Thermal-aware post compilation for VLIW architectures. 606-611 - Arun Kannan, Aviral Shrivastava
A software solution for dynamic stack management on scratch pad memory. 612-617 - Jongeun Lee, Aviral Shrivastava
Compiler-managed register file protection for energy-efficient soft error reduction. 618-623 - Youngchul Cho, Kiyoung Choi:
Code decomposition and recomposition for enhancing embedded software performance. 624-629
Sequential design verification
- Chen-Hsuan Lin, Chun-Yao Wang:
Dependent latch identification in the reachable state space. 630-635 - Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. 636-641 - Jiang Long, Andrew Seawright, Paparao Kavalipati:
Multi-clock SVA synthesis without re-writing. 648-653 - Bing Li, Chris Ka-Kei Kwok:
Automatic formal verification of clock domain crossing signals. 654-659
Scan test generation
- Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Fast false path identification based on functional unsensitizability using RTL information. 660-665 - Zhen Chen, Boxue Yin, Dong Xiang:
Conflict driven scan chain configuration for high transition fault coverage and low test power. 666-671 - Irith Pomeranz, Sudhakar M. Reddy:
Dynamic test compaction for a random test generation procedure with input cube avoidance. 672-677 - Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detectability of internal bridging faults in scan chains. 678-683 - Bing-Chuan Bai
Fault modeling and testing of retention flip-flops in low power designs. 684-689
Designers' forum: analog/RF circuit designs
- Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho:
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. 690-695 - Takashi Kawamoto, Masaru Kokubo:
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA. 696-701 - Nobuyuki Itoh, Mototsugu Hamada:
RF-analog circuit design in scaled SoC. 702-707 - Yuichi Kado
An approach to the RF-LSI design for ubiquitous communication appliances. 708-714
High-level design and scheduling
- Nan Guan
Improving scalability of model-checking for minimizing buffer requirements of synchronous dataflow graphs. 715-720 - Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang:
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization. 721-726 - Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. 727-732 - Hao Shen, Frédéric Pétrot:
Novel task migration framework on configurable heterogeneous MPSoC platforms. 733-738
Emerging design methodologies and applications
- Yexin Zheng, Chao Huang:
A novel Toffoli network synthesis algorithm for reversible logic. 739-744 - Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
A cycle-based synthesis algorithm for reversible logic. 745-750 - Pankaj Bhagawat, Rajballav Dash, Gwan S. Choi:
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study. 751-756 - Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano:
Mapping method for dynamically reconfigurable architecture. 757-762 - Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan:
A criticality-driven microarchitectural three dimensional (3D) floorplanner. 763-768
Verification, test, and yield
- Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao:
Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. 769-774 - Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang:
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. 775-780 - Nicholas Callegari, Pouria Bastani, Li-C. Wang
Path selection for monitoring unexpected systematic timing effects. 781-786 - Mesut Meterelliyoz, Kaushik Roy:
Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. 787-792 - Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. 793-798
Memory systems simulation and optimization
- Li-Pin Chang, Chen-Hui Hsu:
Soft lists: a native index structure for NOR-flash-based embedded devices. 799-804 - Yingchao Zhao
Energy-aware register file re-partitioning for clustered VLIW architectures. 805-810 - Eric Cheung, Harry Hsieh, Felice Balarin:
Memory subsystem simulation in software TLM/T models. 811-816 - Nobuaki Tojo, Nozomu Togawa
Exact and fast L1 cache simulation for embedded systems. 817-822 - Minki Cho, Jason Schlessman, Wayne H. Wolf, Saibal Mukhopadhyay:
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications. 823-828
Emerging technologies
- Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee:
High-speed low-power FinFET based domino logic. 829-834 - M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. 835-840 - Jing Li
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. 841-846 - Charles Augustine, Behtash Behin-Aein, Xuanyao Fong
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. 847-852 - Bao Liu:
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. 853-858
Dependable VLSI: device, design and architecture---how should they cooperate?
- Shuichi Sakai
Dependable VLSI: device, design and architecture: how should they cooperate? 859-860
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