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ISVLSI 2009: Tampa, Florida, USA
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA. IEEE Computer Society 2009, ISBN 978-0-7695-3684-2
- Anthony Chun, Kyle McCanta, Edgar Borrayo Sandoval, Kapil Gulati:
Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOS. 1-6 - H. Md. Shuaeb Fazeel, Leneesh Raghavan, Chandrasekaran Srinivasaraman, Manish Jain:
Reduction of Current Mismatch in PLL Charge Pump. 7-12 - Tuan Vu Cao, Dag T. Wisland, Tor Sverre Lande
, Farshad Moradi
Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency ?S Modulator. 13-18 - Huaxi Gu
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip. 19-24 - Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. 25-30 - Amir Khatib Zadeh, Catherine H. Gebotys:
Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC). 31-36 - Po-Heng Chu, Rung-Bin Lin, Da-Wei Hsu, Yu-Hsing Chen, Wei-Chiu Tseng:
Context-aware Post Routing Redundant Via Insertion. 37-42 - Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson
Efficient Rerouting Algorithms for Congestion Mitigation. 43-48 - Nagarajan Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, Badrinarayanan Ravi:
A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient. 49-54 - Renaud Santoro, Olivier Sentieys
On-the-Fly Evaluation of FPGA-Based True Random Number Generator. 55-60 - Prasanth Mangalagiri, Vijaykrishnan Narayanan:
Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. 61-66 - Jian Huang, Jooheung Lee
A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching. 67-72 - Vijaya Sankara Rao Pasupureddi, Pradip Mandal, Sunil Sachdev:
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect. 73-78 - Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
Modern Floorplanning with Boundary Clustering Constraint. 79-84 - Amit Pande, Joseph Zambreno:
An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform. 85-90 - Koustav Bhattacharya, Nagarajan Ranganathan:
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. 91-96 - Somayeh Timarchi, Keivan Navi, Omid Kavehei
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation. 97-102 - Abinesh Ramachandran, Bharghava Rajaram, Mandalika B. Srinivas:
Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication. 103-108 - Yan Xu, Weichen Liu
On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise. 109-114 - Roger Endrigo Carvalho Porto, Luciano Volcan Agostini
Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding. 115-120 - P. Balasubramanian, Doug A. Edwards:
Dual-Sum Single-Carry Self-Timed Adder Designs. 121-126 - Jins D. Alexander, Vishwani D. Agrawal:
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. 127-132 - Hassan Mostafa
Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits. 133-138 - Dean L. Lewis, Hsien-Hsin S. Lee:
Testing Circuit-Partitioned 3D IC Designs. 139-144 - Weixun Wang, Prabhat Mishra
Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems. 145-150 - Thomas Schilling, Magnus Själander
Scheduling for an Embedded Architecture with a Flexible Datapath. 151-156 - Alexandre Keunecke Ignácio Mendonça, Daniel P. Volpato, José Luís Almada Güntzel, Luiz C. V. dos Santos
Mapping Data and Code into Scratchpads from Relocatable Binaries. 157-162 - Chetan Murthy, Prabhat Mishra
Lossless Compression Using Efficient Encoding of Bitmasks. 163-168 - Debasri Saha, Susmita Sur-Kolay:
Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design. 169-174 - Hao Zheng, Haiqiong Yao, Tomohiro Yoneda:
Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. 175-180 - Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho:
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. 181-186 - David Atienza, Emilio Martinez:
Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip. 187-192 - Sungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan:
A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. 193-198 - Jian Zhang, Shuguo Li:
High Speed Parallel Architecture for Cyclic Convolution Based on FNT. 199-204 - Gennette Gill, John Hansen, Ankur Agiwal, Leandra Vicci, Montek Singh:
A High-Speed GCD Chip: A Case Study in Asynchronous Design. 205-210 - Anshul Singh, Aman Gupta, Sreehari Veeramachaneni
A High Performance Unified BCD and Binary Adder/Subtractor. 211-216 - Hai Li, Haiwen Xi, Yiran Chen, John Stricklin, Xiaobin Wang, Tong Zhang:
Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration. 217-222 - Primoz Pecar, Miha Janez
The Ternary Quantum-dot Cellular Automata Memorizing Cell. 223-228 - Himanshu Thapliyal
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. 229-234 - Caroline Concatto, Debora Matos, Luigi Carro
NoC Power Optimization Using a Reconfigurable Router. 235-240 - Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra:
Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. 241-246 - Mohammad Rafiqul Haider, Syed Kamrul Islam:
Power-Efficient Body-Coupled Self-Cascode LC Oscillator for Low-Power Injection-Locked Transmitter Applications. 247-251 - Sharath Jayaprakash, Nihar R. Mahapatra:
Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters. 252-257 - Swathi Ramasahayam, M. B. Srinivas:
All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. 258-262 - Aarti Choudhary, Sandip Kundu:
A Process Variation Tolerant Self-Compensating Sense Amplifier Design. 263-267 - Santanu Sarkar, Swapna Banerjee:
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. 268-273 - Hariharan Sankaran, Srinivas Katkoori
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs. 274-279 - Thaísa Leal da Silva
Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder. 280-285 - Seokin Hong, Soontae Kim
TEPS: Transient Error Protection Utilizing Sub-word Parallelism. 286-291 - Eduardo Luis Rhod, Luigi Carro
A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies. 292-297 - Chen Dong, Scott Chilstedt, Deming Chen:
Variation Aware Routing for Three-Dimensional FPGAs. 298-303 - Zhimin Chen, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont
Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering. 304-309
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