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ACM Transactions on Architecture and Code Optimization, Volume 19
Volume 19, Number 1, March 2022
- Aditya Ukarande, Suryakant Patidar, Ram Rangan:
Locality-Aware CTA Scheduling for Gaming Applications. 1:1-1:26 - Hongzhi Liu
, Jie Luo, Ying Li, Zhonghai Wu
Iterative Compilation Optimization Based on Metric Learning and Collaborative Filtering. 2:1-2:25 - Muhammad Aditya Sasongko, Milind Chabbi, Mandana Bagheri-Marzijarani, Didem Unat
ReuseTracker: Fast Yet Accurate Multicore Reuse Distance Analyzer. 3:1-3:25 - Yaosheng Fu, Evgeny Bolotin, Niladrish Chatterjee, David W. Nellans, Stephen W. Keckler:
GPU Domain Specialization via Composable On-Package Architecture. 4:1-4:23 - Daeyeal Lee, Bill Lin, Chung-Kuan Cheng:
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing. 5:1-5:21 - Prasanth Chatarasi, Hyoukjun Kwon
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators. 6:1-6:26 - Dennis Rieber, Axel Acosta, Holger Fröning:
Joint Program and Layout Transformations to Enable Convolutional Operators on Specialized Hardware Based on Constraint Programming. 7:1-7:26 - Mengya Lei, Fan Li, Fang Wang, Dan Feng, Xiaomin Zou, Renzhi Xiao:
SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM. 8:1-8:26 - Bang Di, Daokun Hu
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling. 9:1-9:23 - Gururaj Saileshwar
HeapCheck: Low-cost Hardware Support for Memory Safety. 10:1-10:24 - Muhammad Waqar Azhar
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints. 11:1-11:26 - Cesar Gomes
CASHT: Contention Analysis in Shared Hierarchies with Thefts. 12:1-12:27 - Yufei Wang
Optimizing Small-Sample Disk Fault Detection Based on LSTM-GAN Model. 13:1-13:24 - Franyell Silfa
E-BATCH: Energy-Efficient and High-Throughput RNN Batching. 14:1-14:23 - Chen Ding
CARL: Compiler Assigned Reference Leasing. 15:1-15:28
Volume 19, Number 2, June 2022
- Christof Schlaak
Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators. 16:1-16:26 - Kartik Lakshminarasimhan
The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture. 17:1-17:25 - Sharanyan Srikanthan, Sayak Chakraborti
MAPPER: Managing Application Performance via Parallel Efficiency Regulation*. 18:1-18:26 - Athanasios Tziouvaras
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis. 19:1-19:26 - Xingguo Jia
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations. 20:1-20:27 - Mehrzad Nejat
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. 21:1-21:27 - Hugo Pompougnac, Ulysse Beaugnon, Albert Cohen, Dumitru Potop-Butucaru:
Weaving Synchronous Reactions into the Fabric of SSA-form Compilers. 22:1-22:25 - Ghassan Shobaki
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization. 23:1-23:23 - Qihan Wang
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation. 24:1-24:26 - Rakesh Kumar
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. 25:1-25:28 - Nandita Vijaykumar, Ataberk Olgun
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations. 26:1-26:29 - Jing Chen
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. 27:1-27:29 - Chencheng Ye
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory. 28:1-28:26 - George Michelogiannakis
A Case For Intra-rack Resource Disaggregation in HPC. 29:1-29:26
Volume 19, Number 3, September 2022
- Ping Wang
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework. 30:1-30:20 - Marcel Mettler
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors. 31:1-31:24 - Paschalis Mpeis
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization. 32:1-32:25 - Cunlu Li
MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers. 33:1-33:23 - Ziaul Choudhury
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism. 34:1-34:26 - Diksha Moolchandani
Performance and Power Prediction for Concurrent Execution on GPUs. 35:1-35:27 - Ali Jahanshahi
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service. 36:1-36:27 - Peng Xu
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage. 37:1-37:26 - Horng-Ruey Huang
Accelerating Video Captioning on Heterogeneous System Architectures. 38:1-38:25 - David Corbalán-Navarro
Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs. 39:1-39:20 - Shivam Kundan
A Pressure-Aware Policy for Contention Minimization on Multicore Systems. 40:1-40:26 - Johnathan Alsop
A Case for Fine-grain Coherence Specialization in Heterogeneous Systems. 41:1-41:26 - Mohammadreza Soltaniyeh
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication. 42:1-42:26 - Dharanidhar Dang
LiteCON: An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning. 43:1-43:22 - Lokesh Siddhu
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. 44:1-44:25 - Matthew Benjamin Olson
Online Application Guidance for Heterogeneous Memory Systems. 45:1-45:27 - Bruno Chinelato Honorio
Using Barrier Elision to Improve Transactional Code Generation. 46:1-46:23
Volume 19, Number 4, December 2022
- Jiansong Li
An Application-oblivious Memory Scheduling System for DNN Accelerators. 47:1-47:26 - Aditya Narayan
Architecting Optically Controlled Phase Change Memory. 48:1-48:26 - Chao Zhang
ASA: Accelerating Sparse Accumulation in Column-wise SpGEMM. 49:1-49:24 - Aart J. C. Bik, Penporn Koanantakool
Compiler Support for Sparse Tensor Computations in MLIR. 50:1-50:25 - Pierre Michaud
HAIR: Halving the Area of the Integer Register File with Odd/Even Banking. 51:1-51:25 - Amirreza Yousefzadeh
Energy-efficient In-Memory Address Calculation. 52:1-52:16 - Hwisoo So
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults. 53:1-53:26 - Tim Hartley
Just-In-Time Compilation on ARM - A Closer Look at Call-Site Code Consistency. 54:1-54:23 - Erling Rennemo Jellum, Milica Orlandic
Solving Sparse Assignment Problems on FPGAs. 55:1-55:20 - Yuhao Li
Phronesis: Efficient Performance Modeling for High-dimensional Configuration Tuning. 56:1-56:26 - Chandrahas Tirumalasetty
Reducing Minor Page Fault Overheads through Enhanced Page Walker. 57:1-57:26 - Lan Gao
Adaptive Contention Management for Fine-Grained Synchronization on Commodity GPUs. 58:1-58:21 - Ruobing Han
COX : Exposing CUDA Warp-level Functions to CPUs. 59:1-59:25 - Yiding Liu
DynamAP: Architectural Support for Dynamic Graph Traversal on the Automata Processor. 60:1-60:26 - Changwei Zou
Practical Software-Based Shadow Stacks on x86-64. 61:1-61:26
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