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Martin Keim
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2020 – today
- 2024
- [c47]Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra:
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. ETS 2024: 1-10 - [c46]Michele Portolan, Martin Keim, J. F. Coté, Hans-Martin Von Staud:
What Would Interactive Testing With 1687 Look Like? ETS 2024: 1 - [c45]Luc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim:
Combining Built-In Redundancy Analysis with ECC for Memory Testing. ETS 2024: 1-6 - [c44]Jongsin Yun, Sina Bakhtavari Mamaghani, Mehdi B. Tahoori, Christopher Münch, Martin Keim:
MBIST-based weak bit screening method for embedded MRAM. ETS 2024: 1-4 - [c43]Sina Bakhtavari Mamaghani, Jongsin Yun, Martin Keim, Mehdi B. Tahoori:
Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM. VTS 2024: 1-7 - [c42]Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim:
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. VTS 2024: 1-11 - 2023
- [c41]Sina Bakhtavari Mamaghani, Christopher Münch, Jongsin Yun, Martin Keim, Mehdi Baradaran Tahoori:
Smart Hammering: A practical method of pinhole detection in MRAM memories. DATE 2023: 1-6 - [c40]Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim:
Transitioning eMRAM from Pilot Project to Volume Production. ITC 2023: 82-86 - [c39]Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg:
Refreshing the JTAG Family. VTS 2023: 1-7 - 2022
- [j7]Jean-François Côté
, Jeff Fan, Sean Shen, Givargis Danialy, Marcin Lipinski, Michael Garbers
Affordable and Comprehensive Testing of 3-D Stacked Die Devices. IEEE Des. Test 39(5): 17-25 (2022) - [c38]Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo:
IEEE P1687.1: Extending the Network Boundaries for Test. ITC 2022: 382-390 - [c37]Christopher Münch, Jongsin Yun, Martin Keim, Mehdi B. Tahoori:
MBIST-based Trim-Search Test Time Reduction for STT-MRAM. VTS 2022: 1-7 - 2021
- [c36]Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Convolutional Compaction-Based MRAM Fault Diagnosis. ETS 2021: 1-6 - [c35]Christopher Münch, Jongsin Yun, Martin Keim, Mehdi B. Tahoori:
MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM. ETS 2021: 1-6 - [c34]Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim:
Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. ETS 2021: 1-10 - 2020
- [c33]Michele Portolan, Jeff Rearick, Martin Keim:
Linking Chip, Board, and System Test via Standards. ETS 2020: 1-8 - [c32]Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Cyrille Dray, El Mehdi Boujamaa:
MBIST Support for Reliable eMRAM Sensing. ETS 2020: 1-6 - [c31]Manu Baby, Bernd Büttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, Jean-François Côté, Givargis Danialy, Martin Keim, Lori Schramm:
IJTAG Through a Two-Pin Chip Interface. ITC 2020: 1-5 - [c30]Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick:
Modeling Novel Non-JTAG IEEE 1687-Like Architectures. ITC 2020: 1-10 - [c29]Haiying Ma, Ligang Lu, Haitao Qian, Jing Han, Xin Wen, Fanjin Meng, Rahul Singhal, Martin Keim, Yu Huang, Wu Yang:
Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces. ITC 2020: 1-5 - [c28]Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda:
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing. ITC 2020: 1-5
2010 – 2019
- 2018
- [c27]Venkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan:
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions. ITC-Asia 2018: 43-48 - [c26]M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla:
Innovative practices on memory test practice. VTS 2018: 1 - 2017
- [j6]Al Crouch, Michael Laisne, Martin Keim:
Generalizing Access to Instrumentation Embedded in a Semiconductor Device. Computer 50(7): 92-95 (2017) - [c25]Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim:
Adapting an industrial memory BIST solution for testing CAMs. ITC-Asia 2017: 112-117 - 2015
- [c24]Tassanee Payakapan, Senwen Kan, Ken Pham, Kathy Yang, Jean-Francois Cote, Martin Keim, Jennifer Dworak:
A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor. ITC 2015: 1-10 - 2014
- [j5]Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast:
Cell-Aware Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1396-1409 (2014) - [c23]Martin Keim:
Quo Vadis DFT? Aspekte der Technischen Informatik 2014: 51-58 - 2013
- [j4]Martin Keim:
Thinking About Adopting IEEE P1687? IEEE Des. Test 30(5): 36-43 (2013) - [c22]Martin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath:
Industrial Application of IEEE P1687 for an Automotive Product. DSD 2013: 453-461 - 2012
- [c21]Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman
Re-using chip level DFT at board level. ETS 2012: 1
2000 – 2009
- 2008
- [c20]Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10 - [c19]Manish Sharma, Brady Benware, Lei Ling, David Abercrombie, Lincoln Lee, Martin Keim, Huaxing Tang, Wu-Tung Cheng, Ting-Pu Tai, Yi-Jung Chang, Reinhart Lin, Albert Mann:
Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data. ITC 2008: 1-9 - [c18]Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker
Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186 - 2007
- [c17]Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg:
Scan Diagnosis and Its Successful Industrial Applications. ATS 2007: 215 - [c16]Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware:
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. ETS 2007: 145-150 - [c15]Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware:
Silicon Evaluation of Static Alternative Fault Models. VTS 2007: 265-270 - 2006
- [c14]Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware:
A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. ITC 2006: 1-10 - 2004
- [c13]Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski:
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC 2004: 1285-1294 - 2003
- [b1]Martin Keim:
Symbolic methods for testing digital circuits. University of Freiburg, Freiburg im Breisgau, Germany, 2003, pp. 1-196 - [j3]Martin Keim, Rolf Drechsler, Bernd Becker
Polynomial Formal Verification of Multipliers. Formal Methods Syst. Des. 22(1): 39-58 (2003) - 2002
- [c12]Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
Sequential n -Detection Criteria: Keep It Simple. IOLTW 2002: 189 - 2001
- [j2]Martin Keim, Nicole Drechsler, Rolf Drechsler
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electron. Test. 17(1): 37-51 (2001) - 2000
- [c11]Piet Engelke, Bernd Becker, Martin Keim:
A parameterizable fault simulator for bridging faults. ETW 2000: 63-68
1990 – 1999
- 1999
- [j1]Bernd Becker
Hybrid Fault Simulation for Synchronous Sequential Circuits. J. Electron. Test. 15(3): 219-238 (1999) - [c10]Martin Keim, Nicole Drechsler, Bernd Becker:
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. ASP-DAC 1999: 315-318 - [c9]Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
A scalable BIST architecture for delay faults. ETW 1999: 98-103 - 1998
- [c8]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL 1998: 215-221 - 1997
- [c7]Rolf Drechsler, Martin Keim, Bernd Becker:
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. ISMVL 1997: 66-74 - [c6]Rolf Drechsler, Martin Keim, Bernd Becker:
Fault Simulation in Sequential Multi-Valued Logic Networks. ISMVL 1997: 145-152 - [c5]Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor:
Polynomial Formal Verification of Multipliers. VTS 1997: 150-157 - [c4]Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker:
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. VTS 1997: 426-433 - 1996
- [c3]Martin Keim, Bernd Becker, Birgitta Stenner:
On the (non-)resetability of synchronous sequential circuits. VTS 1996: 240-245 - 1995
- [c2]Rolf Krieger, Bernd Becker
Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy. DAC 1995: 339-344 - 1994
- [c1]Rolf Krieger, Bernd Becker, Martin Keim:
A Hybrid Fault Simulator for Synchronous Sequential Circuits. ITC 1994: 614-623
Coauthor Index
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last updated on 2024-07-05 20:15 CEST by the dblp team
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