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Bibhudatta Sahoo 0002
Person information
- affiliation (since 2017): Indian Institute of Technology Kharagpur, Department of Electronics and Electrical Communication Engineering, Kharagpur, India
- affiliation (2016 - 2017): University of Illinois at Urbana-Champaign, IL, USA
- affiliation (2012 - 2016): Amrita University, Department of Electronics and Communication Engineering, Amiratapuri, India
- affiliation (PhD 2009): University of California, Los Angeles, CA, USA
- affiliation (2000 - 2007): Broadcom, Irvine, CA, USA
- affiliation (1998 - 2000): University of Minnesota-Twin Cities, Minneapolis, MN, USA
- affiliation (1994 - 1998): Indian Institute of Technology, Kharagpur, India
Other persons with the same name
- Bibhudatta Sahoo 0001
(aka: Bibhu Datta Sahoo 0001) — National Institute of Technology Rourkela, Odisha, India
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2020 – today
- 2024
- [c36]Rizwan Shaik Peerla, Bibhu Datta Sahoo:
Modular Extended Range Divider For Multi Band Phase Locked Loop. MWSCAS 2024: 310-313 - [c35]Sai Sanjeet, Sanchari Das, Shiuh-Hua Wood Chiang, Masahiro Fujita, Bibhu Datta Sahoo:
Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits -. MWSCAS 2024: 1212-1216 - [c34]Sanchari Das, Bibhu Datta Sahoo:
Closed Form Expression of Input Matching of a Wideband Single-Ended to Differential LNA. VLSID 2024: 168-173 - [i1]Sai Sanjeet, Bibhu Datta Sahoo, Keshab K. Parhi:
SpikePipe: Accelerated Training of Spiking Neural Networks via Inter-Layer Pipelining and Multiprocessor Scheduling. CoRR abs/2406.06879 (2024) - 2023
- [j18]Sai Sanjeet
Energy-Efficient FPGA Implementation of Power-of-2 Weights-Based Convolutional Neural Networks With Low Bit-Precision Input Images. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 741-745 (2023) - [j17]Sai Sanjeet
Transition Point Estimation Using RC-Filtered Square Wave for Calibration of SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1794-1798 (2023) - [j16]Bibhudatta Sahoo
Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction Filters. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3323-3327 (2023) - [j15]Shruti Konwar
Johnson Counter-Based Multiphase Generation for VCO-Based ADC for Direct Digitization of Low Amplitude Sensor Signals. IEEE Trans. Instrum. Meas. 72: 1-4 (2023) - [c33]Sai Sanjeet
Noise Resilience of Reduced Precision Neural Networks. HEART 2023: 114-118 - [c32]Kousik Das, Senorita Deb, Bibhu Datta Sahoo:
A Low Power Cyclic ADC Architecture using Reference Scaling Technique. ISCAS 2023: 1-5 - [c31]Sai Sanjeet, Rahul K. Meena, Bibhu Datta Sahoo, Keshab K. Parhi
IIR Filter-Based Spiking Neural Network. ISCAS 2023: 1-5 - 2022
- [c30]Rizwan Shaik Peerla, Purushothama Chary, Ashudeb Dutta, Bibhu Datta Sahoo:
A Dual VCO Based L5/S Band PLL with Extended Range Divider for IRNSS Application. ISCAS 2022: 1699-1703 - 2021
- [j14]Shouharda Ghosh
Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2257-2261 (2021) - [j13]Shouharda Ghosh
Closed-Form Expression for the Combined Effect of Offset, Gain, Timing, and Bandwidth Mismatch in Time-Interleaved ADCs Using Generalized Sampling. IEEE Trans. Instrum. Meas. 70: 1-12 (2021) - [c29]Sai Sanjeet
Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA. MWSCAS 2021: 112-115 - 2020
- [j12]A. R. Aravinth Kumar
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 212-223 (2020) - [c28]Nagesh Patle
Time-Domain Modeling of Switched-Capacitor Converters with Periodic Inputs. ISCAS 2020: 1-5 - [c27]Harshit Roy, Arkaprova Ray
Deterministic Dither Based Mismatch Characterization of Wide Range of Metal-Oxide-Metal Capacitors. MWSCAS 2020: 880-884
2010 – 2019
- 2019
- [j11]Sesha Sairam Regulagadda
A Packaged Noise-Canceling High-Gain Wideband Low Noise Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 11-15 (2019) - [c26]Alok Keshattiwar, Bibhu Datta Sahoo:
A Systematic Approach to Sizing Capacitors in Split-SAR ADC to Achieve Optimum Redundancy. MWSCAS 2019: 117-120 - [c25]Mayank Palaria, Sai Sanjeet
Adder-Only Convolutional Neural Network with Binary Input Image. MWSCAS 2019: 319-322 - [c24]Radha Krishna Mothukuru, Manish Kumar, Bibhu Datta Sahoo:
A Curvature Compensated Bandgap Circuit Exploiting Temperature Dependence of β. MWSCAS 2019: 509-512 - 2018
- [j10]Vineeth Sarma
A 250-MHz Pipelined ADC-Based fS/4 Noise-Shaping Bandpass ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1785-1794 (2018) - [j9]A. R. Aravinth Kumar, Bibhudatta Sahoo
A Wideband 2-5 GHz Noise Canceling Subthreshold Low Noise Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 834-838 (2018) - [j8]Vineeth Sarma
A DC-to-1-GHz Continuously Tunable Bandpass ADC. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 558-571 (2018) - [c23]Rishabh Govli, Vivek Dixit
1-Transistor-1-Memristor Multilevel Memory Cell. MWSCAS 2018: 508-511 - [c22]Nagaveni S, Bibhudatta Sahoo, Ashudeb Dutta:
Wide Input Range Single Feed RF Energy Harvester. NEWCAS 2018: 144-147 - [c21]Diego James, Abishek T. Kunnath, A. Purushothaman, Bibhudatta Sahoo:
Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier. VLSID 2018: 7-12 - 2017
- [j7]Nevin Alex Jacob, Bibhu Datta Sahoo
Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE. Circuits Syst. Signal Process. 36(12): 4994-5018 (2017) - [j6]Vineeth Sarma, Chithira Ravi, Bibhudatta Sahoo
Achieving Theoretical Limit of SFDR in Pipelined ADCs. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3175-3185 (2017) - [c20]Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 0.7V time-based inductor for fully integrated low bandwidth filter applications. CICC 2017: 1-4 - [c19]Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC 2017: 1-4 - [c18]Rahul Thottathil, Veeresh Babu Vulligaddala, Bibhudatta Sahoo:
CMOS mixed signal SoC for low-side current sensing. ISCAS 2017: 1-4 - [c17]Chithira Ravi, Diego James, Vineeth Sarma, Bibhudatta Sahoo, Amol Inamdar:
Thermal noise canceling pipelined ADC. ISCAS 2017: 1-4 - [c16]Bibhu Datta Sahoo:
Ring oscillator based sub-1V leaky integrate-and-fire neuron circuit. ISCAS 2017: 1-4 - [c15]Chandrasekhar Radhakrishnan, Bibhu Datta Sahoo:
VCO based Nyquist-rate ADC with FVCO of Fs/2. MWSCAS 2017: 1021-1024 - 2016
- [j5]Bibhudatta Sahoo, Amol Inamdar:
Thermal-Noise-Canceling Switched-Capacitor Circuit. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 628-632 (2016) - [c14]Nevin Alex Jacob, Diego James, Bibhu Datta Sahoo:
Full-rate switched capacitor multi-tap DFE for long-tail post-cursor cancellation. MWSCAS 2016: 1-4 - [c13]T. Rahul, Bibhu Datta Sahoo, Veeresh Babu Vulligaddala, Chandra Nyshadham
Bootstrapped leakage suppression switch for switched capacitor circuits with zero input common mode. MWSCAS 2016: 1-4 - [c12]Abishek Thekkeyil Kunnath, Bibhudatta Sahoo:
A Digitally Assisted Radiation Hardened Current Steering DAC. VLSID 2016: 559-560 - 2015
- [c11]Chithira Ravi, Vineeth Sarma, Bibhudatta Sahoo:
At speed digital gain error calibration of pipelined ADCs. NEWCAS 2015: 1-4 - [c10]T. Rahul, Bibhudatta Sahoo, S. Arya, S. J. Parvathy, Veeresh Babu Vulligaddala:
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application. VLSID 2015: 265-270 - 2014
- [j4]Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8 Bit 4 GS/s 120 mW CMOS ADC. IEEE J. Solid State Circuits 49(8): 1751-1761 (2014) - [c9]Bibhudatta Sahoo:
An overview of digital calibration techniques for pipelined ADCs. MWSCAS 2014: 1061-1064 - [c8]Nevin Alex Jacob, Vikas Choudhary, Bibhudatta Sahoo:
A multi-pole single-tap IIR based DFE equalizer topology. NEWCAS 2014: 1-4 - [c7]Chithira Ravi, T. Rahul, Bibhudatta Sahoo:
Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs. VLSID 2014: 569-574 - 2013
- [j3]Bibhudatta Sahoo, Behzad Razavi:
A 10-b 1-GHz 33-mW CMOS ADC. IEEE J. Solid State Circuits 48(6): 1442-1452 (2013) - [c6]Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8-Bit 4-GS/s 120-mW CMOS ADC. CICC 2013: 1-4 - 2012
- [c5]Sounak Roy, Bibhudatta Sahoo, Swapna Banerjee:
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid. ISCAS 2012: 2985-2988 - [c4]Vineeth Sarma, Bibhudatta Sahoo:
Error feedback based noise shaping in a double sampled ADC. NEWCAS 2012: 249-252 - [c3]Bibhudatta Sahoo, Behzad Razavi:
A 10-bit 1-GHz 33-mW CMOS ADC. VLSIC 2012: 30-31
2000 – 2009
- 2009
- [j2]Bibhudatta Sahoo, Behzad Razavi:
A 12-Bit 200-MHz CMOS ADC. IEEE J. Solid State Circuits 44(9): 2366-2380 (2009) - [c2]Bibhudatta Sahoo, Behzad Razavi:
U-PAS: A user-friendly ADC simulator for courses on analog design. MSE 2009: 77-80 - 2003
- [j1]Bibhudatta Sahoo, Keshab K. Parhi
A Low Power Correlator for CDMA Wireless Systems. J. VLSI Signal Process. 35(1): 105-112 (2003) - 2000
- [c1]Bibhudatta Sahoo, Martin Kuhlmann, Keshab K. Parhi:
A low-power correlator. ACM Great Lakes Symposium on VLSI 2000: 153-155
Coauthor Index
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