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Gabriele Manganaro
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2020 – today
- 2024
- [j25]Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits 59(4): 1158-1170 (2024) - [c14]Juzheng Liu, Ayman Shabra, Stacy Ho, Gabriele Manganaro, Mike Shuo-Wei Chen:
A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j24]Gabriele Manganaro, Nicole McFarlane:
New Year Editorial 2023. IEEE Open J. Circuits Syst. 4: 2 (2023) - [j23]Bibhudatta Sahoo, Gabriele Manganaro:
Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction Filters. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3323-3327 (2023) - [c13]Wei-Hsin Tseng, Willy Lin, Chung-Wei Hsu, Chang-Yang Huang, Yu-Sian Lin, Hung-Yi Huang, HsinWei Chen, Sheng-Hui Liao, Kuan-Dar Chen, Jon Strange, Gabriele Manganaro:
A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. ISSCC 2023: 268-269 - [c12]Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j22]Gabriele Manganaro:
Editorial: Where Are We Now and Where Do We Go From Here. IEEE Open J. Circuits Syst. 3: 1-3 (2022) - [c11]Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier:
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. VLSI Technology and Circuits 2022: 100-101 - 2021
- [j21]Gabriele Manganaro:
New Year Editorial. IEEE Open J. Circuits Syst. 2: 1-2 (2021) - [j20]Gabriele Manganaro:
Editorial on the Special Section on the 2021 IEEE International Symposium on Integrated Circuits and Systems. IEEE Open J. Circuits Syst. 2: 434-435 (2021) - 2020
- [j19]Gabriele Manganaro:
Inaugural Issue of the IEEE Open Journal of Circuits and Systems: Welcome Note. IEEE Open J. Circuits Syst. 1: 1-2 (2020)
2010 – 2019
- 2018
- [c10]Gabriele Manganaro:
Emerging data converter architectures and techniques. CICC 2018: 1-8 - [c9]Nevena Rakuljic, Carroll Speir, Eric Otte, Jeff Bray, Corey Petersen, Gabriele Manganaro:
In-situ nonlinear calibration of a RF signal chain. ISCAS 2018: 1-5 - 2017
- [j18]Siddharth Devarajan, Larry Singer, Dan Kelly, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow, Gabriele Manganaro:
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology. IEEE J. Solid State Circuits 52(12): 3204-3218 (2017) - 2014
- [j17]Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. IEEE J. Solid State Circuits 49(2): 405-415 (2014) - 2013
- [j16]Gabriele Manganaro:
Progress update and a look ahead. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 1-2 (2013) - [j15]Gabriele Manganaro:
Outgoing Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3105-3106 (2013) - 2012
- [j14]Gabriele Manganaro:
Incoming Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 1-2 (2012) - [j13]Tor Sverre Lande, Peter T. J. Liang, Gabriele Manganaro, Eduardo A. B. da Silva, Aleksandar Tasic:
Guest Editorial Special Issue on ISCAS 2011. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5): 905 (2012) - [c8]Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. ISSCC 2012: 148-150 - 2011
- [j12]Maged Ghoneima, Yong Lian, Gabriele Manganaro, Shahriar Mirabbasi, Christian Piguet, Wouter A. Serdijn:
Guest Editorial Special Issue on ISCAS 2010. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(7): 1457 (2011) - [j11]Mohab Anis, Howard C. Luong, Gabriele Manganaro:
Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010). IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 1993-1995 (2011) - [c7]Gabriele Manganaro, Domine Leenaerts, Francesco Dantoni, Andrea Baschirotto, Robert Bogdan Staszewski, Nikolaus Klemmer, Seongchol Hong:
Advanced transmitters for wireless infrastructure. ISSCC 2011: 512-513 - 2010
- [j10]Shahriar Mirabbasi, John W. M. Rogers, Gabriele Manganaro:
Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2245-2247 (2010) - [j9]Andrew Marshall, Sakir Sezer, Gabriele Manganaro:
Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3037-3038 (2010)
2000 – 2009
- 2008
- [j8]Ivano Galdi, Edoardo Bonizzoni, Piero Malcovati, Gabriele Manganaro, Franco Maloberti:
40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW. IEEE J. Solid State Circuits 43(7): 1648-1656 (2008) - [j7]Byung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano:
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC. IEEE J. Solid State Circuits 43(12): 2613-2619 (2008) - [c6]Byung Geun Lee, Byung-Moo Min, Gabriele Manganaro, Jonathan W. Valvano:
A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC. ISSCC 2008: 248-249 - 2007
- [c5]J. Li, Robert Leboeuf, Matthew Courcy, Gabriele Manganaro:
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration. CICC 2007: 317-320 - [c4]Ivano Galdi, Edoardo Bonizzoni, Franco Maloberti, Gabriele Manganaro, Piero Malcovati:
Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW. ESSCIRC 2007: 248-251 - 2004
- [j6]Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja:
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer. IEEE J. Solid State Circuits 39(11): 1829-1838 (2004) - 2003
- [j5]Gabriele Manganaro, Sung-Ung Kwak, SeongHwan Cho, Anurag Pulincherry:
A behavioral modeling approach to the design of a low jitter clock source. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 804-814 (2003) - [c3]Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja:
A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer. CICC 2003: 429-432 - 2001
- [c2]Gabriele Manganaro:
An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits. ICECS 2001: 1553-1556 - 2000
- [j4]Gabriele Manganaro, José Pineda de Gyvez:
Nonlinear Computability Based on Chaos. Int. J. Bifurc. Chaos 10(2): 415-430 (2000) - [c1]Irfan A. Chaudrhry, Sung-Ung Kwak, Gabriele Manganaro, Maher Sarraj, T. Lakshmi Viswanathan:
A triple 8b, 80MSPS 3.3 V graphics digitizer. ISCAS 2000: 557-560
1990 – 1999
- 1997
- [j3]Paolo Arena, Riccardo Caponetto, Luigi Fortuna, Gabriele Manganaro:
Cellular neural networks to explore complexity. Soft Comput. 1(3): 120-136 (1997) - 1996
- [j2]Paolo Arena, Salvatore Baglio, Luigi Fortuna, Gabriele Manganaro:
Generation of n-double scrolls via cellular neural networks. Int. J. Circuit Theory Appl. 24(3): 241-252 (1996) - 1995
- [j1]Salvatore Baglio, Luigi Fortuna, Gabriele Manganaro, Rosario Cristaudo:
Complexity in an Industrial flyback converter. J. Circuits Syst. Comput. 5(4): 627-634 (1995)
Coauthor Index
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