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Giuseppe Tagliavini
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2020 – today
- 2024
- [c42]Amirhossein Kiamarzi
, Davide Rossi
QR-PULP: Streamlining QR Decomposition for RISC-V Parallel Ultra-Low-Power Platforms. CF 2024 - [c41]Gabriele Magnani
SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story. CF 2024 - [c40]Benedetta Mazzoni, Luca Bompani, Mattia Orlandi, Simone Benatti, Giuseppe Tagliavini:
Balancing Accuracy and Energy Efficiency on Ultra-Law-Power Platforms for ECG Analysis. COINS 2024: 1-6 - 2023
- [j17]Gianmarco Ottavi
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2450-2463 (2023) - [j16]Enrico Tabanelli
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors. ACM Trans. Embed. Comput. Syst. 22(3): 56:1-56:33 (2023) - [j15]Jie Chen
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 456-469 (2023) - [c39]Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi:
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. DATE 2023: 1-6 - [c38]Seyed Ahmad Mirsalari
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. DATE 2023: 1-2 - [c37]Luca Valente
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. DATE 2023: 1-6 - [c36]Francesco Barchi, Giacomo Pasini, Emanuele Parisi
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). PARMA-DITAM 2023: 3:1-3:12 - [c35]Seyed Ahmad Mirsalari
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS 2023: 1-8 - [c34]Andrea Amidei, Pierangelo Maria Rapa, Giuseppe Tagliavini, Roberto Rabbeni, Paolo Pavan
ANGELS - Smart Steering Wheel for Driver Safety. IWASI 2023: 15-20 - [i18]Jie Chen, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, Davide Rossi:
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters. CoRR abs/2309.01299 (2023) - 2022
- [j14]Davide Rossi
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits 57(1): 127-139 (2022) - [j13]Enrico Tabanelli
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4516-4526 (2022) - [j12]Fabio Montagna
A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. IEEE Trans. Parallel Distributed Syst. 33(5): 1038-1053 (2022) - [c33]Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi:
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. AICAS 2022: 170-173 - [c32]Davide Nadalini
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning. SAMOS 2022: 200-216 - [c31]Benedetta Mazzoni, Giuseppe Tagliavini, Luca Benini, Simone Benatti
An Optimized Heart Rate Detection System Based on Low-Power Microcontroller Platforms for Biosignal Processing. SYSINT 2022: 160-170 - [i17]Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. CoRR abs/2201.08166 (2022) - [i16]Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi:
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. CoRR abs/2201.08656 (2022) - [i15]Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti, Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Geethan Karunaratne, Irem Boybat, Luca Benini, Davide Rossi:
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference. CoRR abs/2206.04796 (2022) - [i14]Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi:
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. CoRR abs/2211.12877 (2022) - [i13]Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi:
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. CoRR abs/2211.14944 (2022) - 2021
- [j11]Benedetta Mazzoni
Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes. IEEE Embed. Syst. Lett. 13(4): 210-213 (2021) - [j10]Alessio Burrello
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. IEEE Trans. Computers 70(8): 1253-1268 (2021) - [j9]Angelo Garofalo
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. IEEE Trans. Emerg. Top. Comput. 9(3): 1489-1505 (2021) - [j8]Florian Glaser
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. IEEE Trans. Parallel Distributed Syst. 32(3): 633-648 (2021) - [c30]Fabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini:
Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUs. ARCS 2021: 167-182 - [c29]Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes. ARITH 2021: 53 - [c28]Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. BioCAS 2021: 1-4 - [c27]Emanuele Parisi
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. DATE 2021: 878-883 - [c26]Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi:
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. ESSCIRC 2021: 267-270 - [c25]Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ICCD 2021: 409-416 - [c24]Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC 2021: 60-62 - [c23]Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini:
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. SAMOS 2021: 16-32 - [i12]Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang, Enrico Tabanelli, Giuseppe Tagliavini, Philippe Ryvlin, Luca Benini, Simone Benatti:
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices. CoRR abs/2106.08008 (2021) - [i11]Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini:
DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors. CoRR abs/2107.09448 (2021) - [i10]Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR abs/2110.09101 (2021) - 2020
- [j7]Giuseppe Tagliavini
FlexFloat: A Software Library for Transprecision Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 145-156 (2020) - [c22]Andrea Borghesi
Combining learning and optimization for transprecision computing. CF 2020: 10-18 - [c21]Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi:
Enabling mixed-precision quantized neural networks in extreme-edge devices. CF 2020: 217-220 - [c20]Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini:
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. DATE 2020: 186-191 - [c19]Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi:
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE 2020: 1067-1072 - [c18]Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ISVLSI 2020: 512-517 - [i9]Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi, Luca Benini, Michela Milano:
Combining Learning and Optimization for Transprecision Computing. CoRR abs/2002.10890 (2020) - [i8]Florian Glaser, Giuseppe Tagliavini, Davide Rossi, Germain Haugou, Qiuting Huang, Luca Benini:
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters. CoRR abs/2004.06662 (2020) - [i7]Nazareno Bruschi, Angelo Garofalo, Francesco Conti, Giuseppe Tagliavini, Davide Rossi:
Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices. CoRR abs/2007.07759 (2020) - [i6]Alessio Burrello, Angelo Garofalo, Nazareno Bruschi, Giuseppe Tagliavini, Davide Rossi, Francesco Conti:
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs. CoRR abs/2008.07127 (2020) - [i5]Fabio Montagna, Stefan Mach, Simone Benatti, Angelo Garofalo, Gianmarco Ottavi, Luca Benini, Davide Rossi, Giuseppe Tagliavini:
A transprecision floating-point cluster for efficient near-sensor data analytics. CoRR abs/2008.12243 (2020) - [i4]Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. CoRR abs/2010.04073 (2020) - [i3]Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. CoRR abs/2011.14325 (2020) - [i2]Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva:
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. CoRR abs/2012.06836 (2020)
2010 – 2019
- 2019
- [j6]Antonio Pullini
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits 54(7): 1970-1981 (2019) - [j5]Victor Javier Kartsch
BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity. IEEE Trans. Biomed. Circuits Syst. 13(5): 893-906 (2019) - [c17]Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA. DATE 2019: 654-657 - 2018
- [j4]Giuseppe Tagliavini
Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators. J. Real Time Image Process. 15(1): 73-92 (2018) - [j3]Giuseppe Tagliavini
Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 982-995 (2018) - [j2]Giuseppe Tagliavini
Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking. IEEE Trans. Parallel Distributed Syst. 29(9): 2150-2163 (2018) - [c16]Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini:
A transprecision floating-point platform for ultra-low power computing. DATE 2018: 1051-1056 - [c15]A. Cristiano I. Malossi
The transprecision computing paradigm: Concept, design, and applications. DATE 2018: 1105-1110 - [c14]Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing. ISCAS 2018: 1-5 - 2017
- [b1]Giuseppe Tagliavini:
Optimization Techniques for Parallel Programming of Embedded Many-Core Computing Platforms. University of Bologna, Italy, 2017 - [i1]Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini:
A Transprecision Floating-Point Platform for Ultra-Low Power Computing. CoRR abs/1711.10374 (2017) - 2016
- [c13]Giuseppe Tagliavini
Enabling OpenVX support in mW-scale parallel accelerators. CASES 2016: 2:1-2:10 - [c12]Giuseppe Tagliavini
Always-on motion detection with application-level error control on a near-threshold approximate computing platform. ICECS 2016: 552-555 - 2015
- [j1]Andrea Marongiu
Simplifying Many-Core-Based Heterogeneous SoC Programming With Offload Directives. IEEE Trans. Ind. Informatics 11(4): 957-967 (2015) - [c11]Davide Rossi
PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium 2015: 1-39 - [c10]Nandhini Chandramoorthy, Giuseppe Tagliavini
Exploring architectural heterogeneity in intelligent vision systems. HPCA 2015: 1-12 - [c9]Giuseppe Tagliavini
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. ISVLSI 2015: 280-285 - [c8]Giuseppe Tagliavini
ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators. MCSoC 2015: 289-296 - [c7]Giuseppe Tagliavini
A framework for optimizing OpenVX applications performance on embedded manycore accelerators. SCOPES 2015: 125-128 - 2014
- [c6]Giuseppe Tagliavini
Supporting localized OpenVX kernel execution for efficient computer vision application development on STHORM many-core platform. Conf. Computing Frontiers 2014: 23:1-23:2 - [c5]Giuseppe Tagliavini
Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators. DASIP 2014: 1-8 - [c4]Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini:
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters. DATE 2014: 1-6 - 2013
- [c3]Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini:
Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters. DATE 2013: 1504-1509 - [c2]Andrea Marongiu, Alessandro Capotondi
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP. MES 2013: 1-8 - 2011
- [c1]Alessio Franceschelli, Paolo Burgio
MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor. Conf. Computing Frontiers 2011: 11
Coauthor Index
[j17] [j16] [j15] [c39] [c38] [c37] [i18] [j14] [j13] [j12] [c33] [c32] [c31] [i17] [i16] [i15] [i14] [i13] [j11] [j9] [j8] [c30] [c29] [c28] [c26] [c25] [c24] [c23] [i12] [i11] [i10] [j7] [c22] [c20] [c19] [c18] [i9] [i8] [i5] [i4] [i3] [j6] [j5] [c17] [j4] [j3] [c16] [c14] [i1] [c13] [c12] [j1] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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last updated on 2024-10-07 21:22 CEST by the dblp team
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