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DATE 2023: Antwerp, Belgium
- Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. IEEE 2023, ISBN 978-3-9819263-7-8
- Jianan Xu, Wenjie Fan, Jan Madsen
, Georgi Plamenov Tanev, Luca Pezzarossa:
AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips. 1-6 - Yichen Jiang, Shuo Wang, Renato Figueiredo, Yier Jin:
Warm-Boot Attack on Modern DRAMs. 1-2 - Jiaxi Zhang, Shenggen Zheng
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. 1-6 - Alexander Schulz-Rosengarten, Reinhard von Hanxleden, Marten Lohstroh, Soroush Bateni, Edward A. Lee:
Polyglot Modal Models through Lingua Franca. 1-2 - Haibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
Split Additive Manufacturing for Printed Neuromorphic Circuits. 1-6 - Youngchang Choi, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang:
MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors. 1-5 - Yixian Shen
Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations. 1-6 - Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie:
Analysis of Quantization Across DNN Accelerator Architecture Paradigms. 1-2 - Weihong Xu, Jaeyoung Kang, Tajana Rosing:
FSL-HD: Accelerating Few-Shot Learning on ReRAM using Hyperdimensional Computing. 1-6 - Lin Chen, Xiao Li, Fan Jiang, Chengeng Li, Jiang Xu:
Smart Knowledge Transfer-based Runtime Power Management. 1-6 - Biresh Kumar Joardar, Krishnendu Chakrabarty:
Attacking ReRAM-based Architectures using Repeated Writes. 1-6 - Alexander Kamkin, Mikhail M. Chupilko, Mikhail Lebedev
High-Level Synthesis versus Hardware Construction. 1-6 - Luca Ezio Pozzoni, Fabrizio Ferrandi
Using High-Level Synthesis to model System Verilog procedural timing controls. 1-6 - Ying Yuan, Zhipeng Tan, Shitong Wei, Lihua Yang, Wenjie Qi, Xuanzhi Wang, Cong Liu:
TPP: Accelerate Application Launch via Two-Phase Prefetching on Smartphone. 1-6 - Samuel Riedel
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. 1-2 - Unmesh D. Bordoloi, Samarjit Chakraborty
Autonomy-driven Emerging Directions in Software-defined Vehicles. 1-6 - Christian Fibich, Martin Horauer, Roman Obermaisser:
Bitstream- Level Interconnect Fault Characterization for SRAM-based FPGAs. 1-2 - Hao-Jan Huang, Wen Sheng Lim, Chia-Heng Tu, Chun-Feng Wu, Yuan-Hao Chang:
Data Freshness Optimization on Networked Intermittent Systems. 1-6 - Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. 1-6 - Biswadeep Chakraborty, Uday Kamal, Xueyuan She, Saurabh Dash, Saibal Mukhopadhyay:
Brain-Inspired Spatiotemporal Processing Algorithms for Efficient Event-Based Perception. 1-6 - Samuel Isuwa
Content- and Lighting-Aware Adaptive Brightness Scaling for Improved Mobile User Experience. 1-2 - Seyed Ahmad Mirsalari
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. 1-2 - Jens Trommer
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. 1-6 - Dilip S. V. Kumar, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede
Low-Cost First-Order Secure Boolean Masking in Glitchy Hardware. 1-2 - Nadia Ibellaatti, Edouard Lepape, Alp Kiliç, Kaya Akyel, Kassem Chouayakh, Fabrizio Ferrandi
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem. 1-5 - Ke Liu
A Lightweight and Adaptive Cache Allocation Scheme for Content Delivery Networks. 1-6 - Michael T. Niemier, Xiaobo Sharon Hu, Liu Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan, Daniel C. Ralph:
Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. 1-10 - Federico Cunico
The Post-pandemic Effects on IoT for Safety: The Safe Place Project. 1-4 - Md. Imtiaz Rashid, Benjamin Carrion Schafer:
MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR. 1-6 - Manil Dev Gomony
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? 1-6 - Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. 1-2 - Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen:
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. 1-2 - Shruti Yadav Narayana, Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras:
A Lightweight Congestion Control Technique for NoCs with Deflection Routing. 1-2 - Mahendra Rathor, Vishesh Mishra
Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers. 1-6 - Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi:
A Novel Delay Calibration Method Considering Interaction between Cells and Wires. 1-6 - Xingyue Qian, Chang Meng
High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table. 1-6 - Kshitij Bhardwaj, Zishen Wan, Arijit Raychowdhury, Ryan A. Goldhahn:
Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving. 1-2 - Yuming Liu, Angel Yanguas-Gil, Sandeep Madireddy, Yanjing Li:
Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Device and Circuit Behaviors. 1-6 - Sandeep Kumar, Abhisek Panda, Smruti R. Sarangi:
Perspector: Benchmarking Benchmark Suites. 1-6 - Yifan Zhang
R-LDPC: Refining Behavior Descriptions in HLS to Implement High-throughput LDPC Decoder. 1-6 - Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang, Ru Huang:
Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. 1-6 - Wenhao Sun, Grace Li Zhang
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. 1-6 - Sai Usha Nagasri Goparaju, L. Lakshmanan, Abhinav Navnit, Rahul Biju, Lovish B, Deepak Gangadharan, Aftab M. Hussain:
Time Series-based Driving Event Recognition for Two Wheelers. 1-2 - Yuanchen Qu, Yu Ma, Pingqiang Zhou:
A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators. 1-6 - Sung-Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen Pham Le
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. 1-6 - Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola:
Exploiting assertions mining and fault analysis to guide RTL-level approximation. 1-2 - Chang Meng
MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis. 1-6 - Fan Yang, Chengqi Xiao, Jun Li, Zhibing Sha, Zhigang Cai, Jianwei Liao:
Out-of-channel data placement for balancing wear-out and I/O workloads in RAID-enabled SSDs. 1-6 - Xabier Iturbe, Nassim Abderrahmane, Jaume Abella
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. 1-6 - Ourania Spantidi, Iraklis Anagnostopoulos:
Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints. 1-6 - Chengcheng Tang, Jie Han:
Hardware Efficient Weight-Binarized Spiking Neural Networks. 1-6 - Shanquan Tian, Shayan Moini, Daniel E. Holcomb, Russell Tessier, Jakub Szefer:
A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs. 1-6 - Shiqing Li, Weichen Liu:
Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches. 1-6 - Yaoxing Chang, Petar Jokic
An Ultra-Low-Power Serial Implementation for Sigmoid and Tanh Using CORDIC Algorithm. 1-2 - Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch, Hans-Joachim Wunderlich:
Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection. 1-2 - Akshay Karkal Kamath
M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search. 1-6 - You Li, Guannan Zhao, Yunqi He, Hai Zhou:
ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection†. 1-6 - Chathura Rajapaksha, Leila Delshadtehrani, Manuel Egele, Ajay Joshi:
SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels. 1-6 - David van Son, Floran de Putter, Sebastian Vogel, Henk Corporaal:
BOMP- NAS: Bayesian Optimization Mixed Precision NAS. 1-2 - Ziyue Zheng, Yangdi Lyu:
STSearch: State Tracing-based Search Heuristics for RTL Validation. 1-6 - Chaitali Sathe, Yiorgos Makris, Benjamin Carrion Schafer:
MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS. 1-6 - Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal
Securing a RISC-V architecture: A dynamic approach. 1-5 - Fangxin Liu, Wenbo Zhao, Zongwu Wang, Xiaokang Yang, Li Jiang:
SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN Acceleration. 1-2 - Daeyeon Kim, Jakang Lee, Seokhyeong Kang:
Routability Prediction using Deep Hierarchical Classification and Regression. 1-2 - Wenlu Xue, Jinyu Bai, Sifan Sun, Wang Kang:
Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement. 1-6 - Zejian Liu, Kun Zhao, Jian Cheng:
TBERT: Dynamic BERT Inference with Top-k Based Predictors. 1-6 - Gia Bao Thieu
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. 1-6 - Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic:
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs. 1-6 - Dimitris Theodoropoulos, Olivier Michel, Pavlos Malakonakis, Konstantinos Georgopoulos, Giovanni Isotton
Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project Intermediate stage. 1-4 - Jingdian Ming, Yongbin Zhou, Wei Cheng, Huizhong Li:
Table Re-Computation Based Low Entropy Inner Product Masking Scheme. 1-6 - Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron
Hardware Trojans in eNVM Neuromorphic Devices. 1-6 - Sandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu:
A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication. 1-6 - Zhuanhao Wu, Marat Bekmyrza, Nachiket Kapre, Hiren D. Patel:
Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems. 1-6 - Zachery Utt, Daniel Volya
Quantum Measurement Discrimination using Cumulative Distribution Functions. 1-6 - Songran Liu, Mingsong Lv, Wei Zhang, Xu Jiang, Chuancai Gu, Tao Yang, Wang Yi, Nan Guan
Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT Devices. 1-6 - Van-Phu Ha, Olivier Sentieys:
Maximizing Computing Accuracy on Resource-Constrained Architectures. 1-6 - Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian, Mohammad Moshiur Rahman:
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits. 1-6 - Qisheng Jiang
Atomic but Lazy Updating with Memory-mapped Files for Persistent Memory. 1-6 - Yujin Zheng, Alex Bystrov
A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating. 1-2 - Tianyu Fu
CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory. 1-6 - Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, J. Guerrero, Luca Sterpone, Matteo Sonza Reorda
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections. 1-6 - Ayesha Siddique, Khaza Anuarul Hoque:
Improving Reliability of Spiking Neural Networks through Fault Aware Threshold Voltage Optimization. 1-6 - Dwaipayan Choudhury, Ananth Kalyanaraman, Partha Pande:
GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing. 1-6 - Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee:
Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. 1-2 - Dina A. Moussa, Michael Hefenbrock, Mehdi B. Tahoori:
Compact Test Pattern Generation For Multiple Faults In Deep Neural Networks. 1-2 - Nora Sperling, Alex Bendrick, Dominik Stöhrmann
Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. 1-6 - Mahta Mayahinia, Hsiao-Hsuan Liu, Subrat Mishra, Zsolt Tokei
Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes. 1-6 - Huimin Li, Nele Mentens
Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions. 1-6 - Chao Lu, Christian Pilato, Kanad Basu:
Towards High-Level Synthesis of Quantum Circuits. 1-6 - Simeng Zheng, Chih-Hui Ho, Wenyu Peng, Paul H. Siegel:
Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets. 1-6 - Shashwat Khandelwal, Anneliese Walsh, Shanker Shreejith
Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks. 1-2 - Ting-Yu Yeh, Yueh Cho, Yung-Chih Chen:
An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification. 1-6 - Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Yisong Chang, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou Shan:
MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior. 1-6 - Wenhui Ou, Zhuoyu Wu
COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions. 1-6 - Mohammed Nabeel, Deepraj Soni, Mohammed Ashraf, Mizan Abraha Gebremichael, Homer Gamil, Eduardo Chielle, Ramesh Karri
CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution. 1-2 - René Griessl, Florian Porrmann, Nils Kucza, Kevin Mika, Jens Hagemeyer, Martin Kaiser
Evaluation of heterogeneous AIoT Accelerators within VEDLIoT. 1-6 - Thomas Dalgaty, Thomas Mesquida, Damien Joubert, Amos Sironi, Cyrille Soubeyrat, Pascal Vivet
The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks. 1-6 - Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing. 1-6 - Fikret Basic
Establishing Dynamic Secure Sessions for ECQV Implicit Certificates in Embedded Systems. 1-6 - Bernhard Lippmann, Joel Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, Michaela Brunner, Tim Music, Michael Pehl, Tauseef Siddiqui, Ralf Brederlow
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations. 1-6 - Katharina Ruep, Daniel Große:
Improving Design Understanding of Processors leveraging Datapath Clustering. 1-2 - Masoomeh Karami, Sajad Shahsavari, Eero Immonen
A Coupled Battery State-of-Charge and Voltage Model for Optimal Control Applications. 1-2 - Anika Christmann, Robin Hapka, Rolf Ernst:
Formal Analysis of Timing Diversity for Autonomous Systems. 1-6 - Marcello Traiola, Angeliki Kritikakou, Olivier Sentieys:
A machine-learning-guided framework for fault-tolerant DNNs. 1-2 - Thilo L. Fischer, Heiko Falk:
WCET Analysis of Shared Caches in Multi -Core Architectures using Event-Arrival Curves. 1-2 - Ludovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer
EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications. 1-6 - Pascal Nasahl, Martin Unterguggenberger, Rishub Nagpal, Robert Schilling, David Schrammel, Stefan Mangard:
SCFI: State Machine Control-Flow Hardening Against Fault Attacks. 1-6 - Aggelos Ferikoglou, Argyris Kokkinis, Dimitrios Danopoulos, Ioannis Oroutzoglou, Anastassios Nanos
The SERRANO platform: Stepping towards seamless application development & deployment in the heterogeneous edge-cloud continuum. 1-4 - Lihua Yang, Zhipeng Tan, Fang Wang, Yang Xiao
FAGC: Free Space Fragmentation Aware GC Scheme based on Observations of Energy Consumption. 1-2 - Alberto Bombardelli
Metric Temporal Logic with Resettable Skewed Clocks. 1-6 - Hongsun Jang, Jaewon Jung, Jaeyong Song
Pipe-BD: Pipelined Parallel Blockwise Distillation. 1-6 - Onat Güngör, Tajana Rosing, Baris Aksanli
HD-I-IoT: Hyperdimensional Computing for Resilient Industrial Internet of Things Analytics. 1-6 - Shivam Aggarwal, Kuluhan Binici, Tulika Mitra:
Chameleon: Dual Memory Replay for Online Continual Learning on Edge Devices. 1-6 - Prachi Shukla, Derrick Aguren, Tom Burd, Ayse K. Coskun, John Kalamatianos:
Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads. 1-6 - Jari Nurmi
SPHERE-DNA: Privacy-Preserving Federated Learning for eHealth. 1-6 - Hongwei Cui, Shuhao Liang, Yujie Cui
A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation. 1-2 - Guannan Guo, Tsung-Wei Huang, Martin D. F. Wong:
Fast STA Graph Partitioning Framework for Multi-GPU Acceleration. 1-6 - Tathagata Srimani
Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits. 1-6 - Franyell Silfa, José-María Arnau, Antonio González:
Exploiting Kernel Compression on BNNs. 1-6 - Chou-Ying Hsieh, Po-Hsiu Cheng, Chia-Ming Chang, Sy-Yen Kuo:
A Decentralized Frontier Queue for Improving Scalability of Breadth-First-Search on GPUs. 1-6 - Hyunsu Chae
ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. 1-6 - Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noël, Bastien Giraud, Marc Bocquet, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Binary ReRAM-based BNN first-layer implementation. 1-6 - Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. 1-2 - Youngbin Kim
Liveness-Aware Checkpointing of Arrays for Efficient Intermittent Computing. 1-6 - Youbiao He, Hebi Li, Ge Luo, Forrest Sheng Bao:
Two-stage PCB Routing Using Polygon-based Dynamic Partitioning and MCTS. 1-2 - Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar:
Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. 1-2 - Enrico Fraccaroli
Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle Networks. 1-6 - Mohammadreza Barzegaran
The FORA European Training Network on Fog Computing for Robotics and Industrial Automation. 1-6 - Duy-Thanh Nguyen, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
DeepCAM: A Fully CAM-based Inference Accelerator with Variable Hash Lengths for Energy-efficient Deep Neural Networks. 1-6 - Christopher Leet, Chanwook Oh, Michele Lora, Sven Koenig, Pierluigi Nuzzo:
Co-Design of Topology, Scheduling, and Path Planning in Automated Warehouses. 1-6 - Sebastian Karl, Arne Symons
Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems. 1-6 - Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback
Device-Aware Test for Back-Hopping Defects in STT-MRAMs. 1-6 - Nick van de Waterlaat, Sebastian Vogel, Hiram Rayo Torres Rodriguez, Willem P. Sanberg, Gerardo Daalderop:
Quantization-Aware Neural Architecture Search with Hyperparameter Optimization for Industrial Predictive Maintenance Applications. 1-2 - Yu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu:
Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory. 1-6 - Rongliang Fu, Junying Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho, Olivia Chen
BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. 1-2 - Gopikrishnan Raveendran Nair, Han-Sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, Yu Cao:
FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix. 1-6 - Jiaqi Wang, Mark Daniel Alea
End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification. 1-6 - Ru Xie, Jing Yang, Jingying Li, Liming Wang:
ImpactTracer: Root Cause Localization in Microservices Based on Fault Propagation Modeling. 1-6 - Martin Hurta
ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. 1-2 - Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz
Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. 1-6 - Xinyan Zhang
Multidimensional Features Helping Predict Failures in Production SSD-Based Consumer Storage Systems. 1-6 - Shreesha Sreedhara, Jaijeet Roychowdhury, Joachim Wabnig, K. Pavan Srinath:
Digital Emulation of Oscillator Ising Machines. 1-2 - Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. 1-6 - Heba Salem, Nigel P. Topham:
Run-time integrity monitoring of untrustworthy analog front-ends. 1-6 - Kailash Prasad, Sai Shubham, Aditya Biswas, Joycee Mekie:
Process Variation Resilient Current-Domain Analog In Memory Computing. 1-2 - Jeferson González-Gómez
The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures. 1-6 - RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang:
Expanding In-Cone Obfuscated Tree for Anti SAT Attack. 1-6 - William Fornaciari
Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems. 1-6 - Shvetank Prakash, Tim Callahan, Joseph Bushagour, Colby R. Banbury, Alan V. Green, Pete Warden, Tim Ansell, Vijay Janapa Reddi:
CFU Playground: Want a faster ML processor? Do it yourself! 1-2 - Wenqi Lou
NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA. 1-6 - Halima Bouzidi
HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling. 1-6 - Hyeong Kon Bae, Myung Jae Chung, Young-Ho Gong, Sung Woo Chung:
Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience. 1-6 - Eunji Kwon, Haena Song, Jihye Park, Seokhyeong Kang:
Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision. 1-6 - Dengwei Zhao
DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network. 1-2 - Yun Huang
SERICO: Scheduling Real-Time I/O Requests in Computational Storage Drives. 1-6 - Yungang Pan
Resource Optimization with 5G Configured Grant Scheduling for Real-Time Applications. 1-2 - Seokho Lee, Younghyun Lee, Hyejun Kim, Taehoon Kim, Yongjun Park:
Block Group Scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory Allocation. 1-6 - Amro Eldebiky, Grace Li Zhang
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation. 1-6 - Jinsung Youn, Luca Ramini, Zeqin Lu, Ahsan Alam, James Pond, Marco Fiorentino, Raymond G. Beausoleil:
Multiphysics Design and Simulation Methodology for Dense WDM Silicon Photonics. 1-2 - Sergey Mileiko, Oktay Cetinkaya
Stateful Energy Management for Multi-Source Energy Harvesting Transient Computing Systems. 1-6 - Haena Song, Jongho Yoon, Dohun Kim, Eunji Kwon, Tae-Hyun Oh, Seokhyeong Kang:
FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks. 1-6 - Johnson Loh, Tobias Gemmeke:
Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals. 1-6 - Changhai Man, Cheng Chang, Chenchen Ding, Ao Shen, Hongwei Ren, Ziyi Guan, Yuan Cheng, Shaobo Luo, Rumin Zhang, Ngai Wong, Hao Yu:
RankSearch: An Automatic Rank Search Towards Optimal Tensor Compression for Video LSTM Networks on Edge. 1-2 - Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang:
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. 1-6 - David Rodriguez, Rafael Tornero
Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms. 1-6 - Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima:
Out-of-Step Pipeline for Gather/Scatter Instructions. 1-2 - Chao Fang
CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks. 1-2 - Hao Kong, Xiangzhong Luo, Shuo Huai, Di Liu, Ravi Subramaniam, Christian Makaya, Qian Lin, Weichen Liu:
EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI. 1-2 - Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi:
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures. 1-6 - Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. 1-2 - Harsh Sharma
Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures. 1-6 - Nathan Roussel, Olivier Potin, Jean-Max Dutertre, Jean-Baptiste Rigaud:
Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation. 1-6 - Jaume Abella
SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI. 1-6 - Alessio Burrello, Matteo Risso, Noemi Tomasello, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari
Energy-efficient Wearable-to-Mobile Offload of ML Inference for PPG-based Heart-Rate Estimation. 1-6 - Heng Zhou, Bing Wu, Huan Cheng, Wei Zhao, Xueliang Wei, Jinpeng Liu, Dan Feng, Wei Tong:
ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep Learning. 1-6 - Timothy J. Baker, John P. Hayes:
Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior. 1-6 - Hamza Errahmouni Barkam, SungHeon Eavn Jeon, Calvin Yeung, Zhuowen Zou, Xun Jiao, Mohsen Imani:
Comprehensive Analysis of Hyperdimensional Computing Against Gradient Based Attacks. 1-2 - Jiseung Kim, Hyunsei Lee, Mohsen Imani, Yeseong Kim:
Efficient Hyperdimensional Learning with Trainable, Quantizable, and Holistic Data Representation. 1-6 - Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu:
Efficient Design Rule Checking with GPU Acceleration. 1-2 - Md Rafid Muttaki
RTLock: IP Protection using Scan-Aware Logic Locking at RTL. 1-6 - Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder
Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems. 1-2 - Xu Jiang, Xiantong Luo, Nan Guan
Analysis and Optimization of Worst-Case Time Disparity in Cause-Effect Chains. 1-6 - Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities. 1-6 - Sebastian Brandhofer, Jinwoong Kim, Siyuan Niu, Nicholas T. Bronn:
SAT-Based Quantum Circuit Adaptation. 1-6 - Biruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter, Luca P. Carloni:
PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs. 1-6 - Zihao Chen, Fan Yang, Li Shang, Xuan Zeng:
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search. 1-6 - Marco Gonzalez
Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW. 1-6 - Jonti Talukdar, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty:
Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation. 1-2 - Qiang Liu, Longtao Guo, Honghui Tang:
Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack. 1-6 - Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian Ghadikolaei, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. 1-2 - Zhengang Chen, Guohui Wang, Zhi-Ping Shi, Yong Guan, Tianyu Wang
Region-based Flash Caching with Joint Latency and Lifetime Optimization in Hybrid SMR Storage Systems. 1-6 - Rolf Drechsler, Alireza Mahzoon:
Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. 1-2 - Songqiao Cui
Efficient Software Masking of AES through Instruction Set Extensions. 1-6 - Qingsong Zhu, Qiang Cao, Jie Yao:
UHS: An Ultra-fast Hybrid Storage Consolidating NVM and SSD in Parallel. 1-6 - Lorenzo Lamberti
Bio-inspired Autonomous Exploration Policies with CNN-based Object Detection on Nano-drones. 1-6 - Shui Jiang, Seetal Potluri, Tsung-Yi Ho:
Scalable Scan-Chain-Based Extraction of Neural Network Models. 1-6 - Shixin Zhao, Songyun Qu, Ying Wang, Yinhe Han:
ENASA: Towards Edge Neural Architecture Search based on CIM acceleration. 1-2 - Changjin Koo, Jaegeun Park, Taewook Ahn, Hongsuk Kim, Jong-Chan Kim
Phalanx: Failure-Resilient Truck Platooning System. 1-6 - Argyris Kokkinis, Georgios Zervakis, Kostas Siozios, Mehdi B. Tahoori, Jörg Henkel:
Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons. 1-2 - Florian Klemme, Sami Salamin, Hussam Amrouch:
Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows. 1-6 - Nguyen Anh Vu Doan, Arda Yüksel, Chih-Hong Cheng:
Butterfly Effect Attack: Tiny and Seemingly Unrelated Perturbations for Object Detection. 1-6 - Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Floating Point Adders. 1-2 - Soyed Tuhin Ahmed, Kamal Danouchi
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. 1-6 - Laurent Fesquet, Rosalie Tran, Xavier Lesage, Mohamed Akrarai, Stéphane Mancini, Gilles Sicard:
Low-Throughput Event-Based Image Sensors and Processing. 1-6 - Longxing Jiang, David Aledo
Jumping Shift: A Logarithmic Quantization Method for Low-Power CNN Acceleration. 1-6 - Jingquan Ge, Yuekang Li
PumpChannel: An Efficient and Secure Communication Channel for Trusted Execution Environment on ARM-FPGA Embedded SoC. 1-6 - Wenhao Sun, Grace Li Zhang
Class-based Quantization for Neural Networks. 1-6 - Gabriel H. Loh, Raja Swaminathan:
The Next Era for Chiplet Innovation. 1-6 - Abhimanyu Rajeshkumar Bambhaniya
Proteus : HLS-based NoC Generator and Simulator. 1-6 - Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang, Yu Huang, Jianye Hao:
TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. 1-5 - Sayandeep Saha, Prasanna Ravi, Dirmanto Jap, Shivam Bhasin:
Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP. 1-6 - Zhouxuan Peng, Dan Feng, Jianxi Chen, Jing Hu
AGDM: An Adaptive Granularity Data Migration Strategy for Hybrid Memory Systems. 1-6 - Niko Zurstraßen
par-gem5: Parallelizing gem5's Atomic Mode. 1-6 - Kemal Çaglar Coskun
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits. 1-6 - Jinhua Cui, Yiyun Yin, Congcong Chen, Jiliang Zhang:
Spoiler-Alert: Detecting Spoiler Attacks Using a Cuckoo Filter. 1-6 - Zhidan Zheng
XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers. 1-6 - Behnaz Ranjbar
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level. 1-10 - Kevin Kai-Chun Chang, Xiangguo Liu, Chung-Wei Lin, Chao Huang, Qi Zhu:
A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication Disturbance. 1-6 - Giovanni Mezzina, Arturo Amendola, Mario Barbareschi, Salvatore De Simone, Grazia Mascellaro, Alberto Moriconi, Cataldo Luciano Saragaglia, Diana Serra
A Step Toward Safe Unattended Train Operations: A Pioneer Vital Control Module. 1-4 - Clément Metz
Lattice Quantization. 1-2 - Behnaz Ranjbar
Motivating Agent-Based Learning for Bounding Time in Mixed-Criticality Systems. 1-2 - Tom Glint, Manu Awasthi, Joycee Mekie:
REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet. 1-6 - Taehoon Kim, Yoona Lee, Woo-Seok Choi:
Fast Performance Evaluation Methodology for High-speed Memory Interfaces. 1-6 - Sercan Aygun, M. Hassan Najafi, Mohsen Imani:
A Linear-Time, Optimization-Free, and Edge Device-Compatible Hypervector Encoding. 1-2 - Wantong Li, Yandong Luo, Shimeng Yu:
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers. 1-6 - Lukas Esterle, Nikil D. Dutt, Christian Gruhl, Peter R. Lewis, Lucio Marcenaro, Carlo S. Regazzoni, Axel Jantsch:
Self-awareness in Cyber-Physical Systems: Recent Developments and Open Challenges. 1-6 - Benjamin Rouxel, Christopher Brown
The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems. 1-6 - Sascha Schmalhofer, Marwin Möller, Nikoletta Katsaouni
Debugging Low Power Analog Neural Networks for Edge Computing. 1-2 - Jooho Wang, Sunwoo Kim, Junsu Heo, Chester Sungchung Park:
eF2lowSim: System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural Networks. 1-6 - Zhiqiang Liu
Computing Effective Resistances on Large Graphs Based on Approximate Inverse of Cholesky Factor. 1-6 - Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Processor Verification using Symbolic Execution: A RISC-V Case-Study. 1-6 - Hanbo Sun, Tongxin Xie, Zhenhua Zhu, Guohao Dai, Huazhong Yang, Yu Wang:
Minimizing Communication Conflicts in Network-On-Chip Based Processing-In-Memory Architecture. 1-6 - Ranyang Zhou, Sepehr Tabrizchi, Mehrdad Morsali, Arman Roohi, Shaahin Angizi:
P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer Protection. 1-6 - Jianbo Liu, Boyang Cheng
Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing. 1-6 - Honglan Zhan
High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation. 1-6 - Uzair Sharif, Daniel Mueller-Gritschneder
Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications. 1-6 - Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini, Davide Rossi:
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture. 1-6 - Jun Yin, Stefano Damiano
Real-Time Acoustic Perception for Automotive Applications. 1-6 - Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor:
SheLL: Shrinking eFPGA Fabrics for Logic Locking. 1-6 - Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. 1-2 - Jie Ran, Rui Lin, Jason Chun Lok Li, Jiajun Zhou
PECAN: A Product-Quantized Content Addressable Memory Network. 1-6 - Mufan Xiang, Yongjian Li, Yongxin Zhao:
ChiselFV: A Formal Verification Framework for Chisel. 1-6 - Sung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun
ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training. 1-6 - Minxuan Zhou, Xuan Wang, Tajana Rosing:
OverlaPIM: Overlap Optimization for Processing In-Memory Neural Network Acceleration. 1-6 - Alexandra Küster, Rainer Dorsch, Christian Haubelt:
Structural Generation of Virtual Prototypes for Smart Sensor Development in SystemC-AMS from Simulink Models. 1-2 - Yeqi Wei, Wenjing Rao, Natasha Devroye:
APUF Production Line Faults: Uniqueness and Testing. 1-6 - Toygun Basaklar, Yigit Tuncel, Suat Gumussoy, Ümit Y. Ogras:
GEM-RL: Generalized Energy Management of Wearable Devices using Reinforcement Learning. 1-6 - Taha Shahroodi, Raphael Cardoso, Mahdi Zahedi, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui:
Lightspeed Binary Neural Networks using Optical Phase-Change Materials. 1-2 - Zhenhua Tan, Linbo Long, Renping Liu, Congming Gao, Yi Jiang, Yan Liu:
Optimizing Data Migration for Garbage Collection in ZNS SSDs. 1-2 - Ziqing Zeng
Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications. 1-6 - Yuyang Ye
Fast and Accurate Wire Timing Estimation Based on Graph Learning. 1-6 - Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim:
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. 1-6 - Julian Demicoli, Laurin Prenzel, Sebastian Steinhorst:
Autonomous Hyperloop Control Architecture Design using MAPE-K. 1-6 - Li-Chen Wang, Shao-Yun Fang:
Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement. 1-2 - Chung-Hsuan Tung, Biresh Kumar Joardar, Partha Pratim Pande, Janardhan Rao Doppa, Hai Helen Li, Krishnendu Chakrabarty:
Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars. 1-6 - Chonghan Lee, Rita Brugarolas Brufau, Ke Ding, Vijaykrishnan Narayanan:
Token Adaptive Vision Transformer with Efficient Deployment for Fine-Grained Image Recognition. 1-6 - Yuhan Chen, Alireza Khadem, Xin He, Nishil Talati, Tanvir Ahmed Khan, Trevor N. Mudge:
PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows. 1-6 - Thomas Kotrba, Martin Lechner, Omair Sarwar, Axel Jantsch:
Multispectral Feature Fusion for Deep Object Detection on Embedded NVIDIA Platforms. 1-2 - Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. 1-6 - Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jerónimo Castrillón, Antonio Carlos Schneider Beck:
Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs. 1-6 - Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi:
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. 1-6 - Marco Bertuletti
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor. 1-6 - Daniel Sturm, Sajjad Moazeni:
Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration. 1-6 - Tao Yang, Hui Ma, Yilong Zhao
PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy. 1-6 - Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. 1-6 - Yiyue Jiang, Andrius Vaicaitis, Miriam Leeser, John Dooley:
Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems. 1-2 - Luca Valente
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. 1-6 - Hany Abdelmaksoud, Zain Alabedin Haj Hammadeh
DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation. 1-2 - Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. 1-2 - Fabian Kempf, Julian Höfer
The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective. 1-6 - Nathaniel Bleier
Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible Electronics. 1-6 - Qingqiang He, Nan Guan
On the Degree of Parallelism in Real-Time Scheduling of DAG Tasks. 1-6 - Cristian Turetta, Geri Skenderi, Luigi Capogrosso
Towards Deep Learning-based Occupancy Detection Via WiFi Sensing in Unconstrained Environments. 1-6 - Md Faizul Bari, Meghna Roy Chowdhury, Shreyas Sen:
Long Range Detection of Emanation from HDMI Cables Using CNN and Transfer Learning. 1-6 - Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim:
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. 1-6 - Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo:
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. 1-6 - Sina Bakhtavari Mamaghani, Christopher Münch, Jongsin Yun, Martin Keim, Mehdi Baradaran Tahoori:
Smart Hammering: A practical method of pinhole detection in MRAM memories. 1-6 - Muhammad Abdullah Hanif, Muhammad Shafique
Reduce: A Framework for Reducing the Overheads of Fault-Aware Retraining. 1-2 - Syed Tihaam Ahmad, Ayesha Siddique, Khaza Anuarul Hoque:
Security-Aware Approximate Spiking Neural Networks. 1-6 - Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun:
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. 1-6 - Yifeng Zhai, Bing Li, Bonan Yan, Jing Wang:
STAR: An Efficient Softmax Engine for Attention Model with RRAM Crossbar. 1-2 - Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara:
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. 1-2 - Sirui Qi
MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms. 1-6 - Zhao Yang, Qingshuang Sun:
Mitigating Heterogeneities in Federated Edge Learning with Resource- independence Aggregation. 1-2 - Andreas Kosmas Kakolyris
RoaD-RuNNer: Collaborative DNN partitioning and offloading on heterogeneous edge systems. 1-6 - Shao-Ching Huang, Kai-En Lin, Cheng-Yen Kuo, Li-Heng Lin, Muhammed O. Sayin
Reinforcement-Learning-Based Job-Shop Scheduling for Intelligent Intersection Management. 1-6 - Yigit Tuncel, Toygun Basaklar, Mackenzie Smithyman, João Dórea, Vinícius Nunes De Gouvêa, Younghyun Kim, Ümit Y. Ogras:
Towards Smart Cattle Farms: Automated Inspection of Cattle Health with Real-Life Data. 1-2 - Priyanka Golia, Subhajit Roy, Kuldeep S. Meel:
Synthesis with Explicit Dependencies. 1-6 - Dirk Elias, Dirk Ziegenbein, Philipp Mundhenk, Arne Hamann, Anthony Rowe:
The Cyber-Physical Metaverse - Where Digital Twins and Humans Come Together. 1-2 - Sanghwi Kim, Hyejin Shin, Hyunkyu Kim:
Two-Stream Neural Network for Post-Layout Waveform Prediction. 1-2 - Hongyang Pan, Zhufei Chu:
Exact Synthesis Based on Semi-Tensor Product Circuit Solver. 1-6 - Sanket Shukla, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao:
Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks. 1-6 - Sizhe Zhang, Zhao Wang, Xun Jiao:
Adversarial Attack on Hyperdimensional Computing-based NLP Applications. 1-6 - Rasmus Adler
Autonomous System Design Session - Benefits, Challenges and Risks in Various Application Domains. 1-2 - Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. 1-2 - Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. 1-6 - Yingxue Gao, Teng Wang, Lei Gong, Chao Wang, Xi Li, Xuehai Zhou:
FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAs. 1-6 - Haibin Zhao, Brojogopal Sapui, Michael Hefenbrock, Zhidong Yang, Michael Beigl, Mehdi B. Tahoori:
Highly-Bespoke Robust Printed Neuromorphic Circuits. 1-6 - Jiazhi Jiang, Zijiang Huang, Dan Huang, Jiangsu Du, Yutong Lu:
Accelerating Inference of 3D-CNN on ARMMany-core CPU via Hierarchical Model Partition. 1-2 - Ilya Tuzov, David de Andrés
BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. 1-6 - Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. 1-6 - Anstasios Dimitriou, Mingyu Hu, Jonathon S. Hare, Geoff V. Merrett:
Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs. 1-2 - Mahdi Zahedi, Geert Custers, Taha Shahroodi, Georgi Gaydadjiev
SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph Processing. 1-6 - Benedikt Ohse
Efficient Approximation of Performance Spaces for Analog Circuits via Multi-Objective Optimization. 1-6 - Hasini Witharana
Dynamic Refinement of Hardware Assertion Checkers. 1-6 - Jihun Park, Donghun Jeong
UVMMU: Hardware-Offloaded Page Migration for Heterogeneous Computing. 1-6 - Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang:
An Automated Verification Framework for HalideIR-Based Compiler Transformations. 1-6 - Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek:
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. 1-6 - Clement Türck, Kamel-Eddine Harabi, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Marc Bocquet, Jean-Michel Portal, Damien Querlioz:
Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors. 1-2 - Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux:
Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials. 1-2 - Dewmini Sudara Marakkalage, Giovanni De Micheli:
Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach. 1-6 - Febin Sunny, Ebadollah Taheri, Mahdi Nikdast, Sudeep Pasricha:
Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics. 1-6 - Kaveh Shamsi, Rajesh Kumar Datta:
TIPLock: Key-Compressed Logic Locking using Through-Input-Programmable Lookup-Tables. 1-2 - Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, Yinhe Han, Lei Zhang:
Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. 1-6 - Rui Guo
EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction. 1-6 - Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao, Yue Zhang:
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation. 1-6 - Ashitabh Misra, Jacob Laurel, Sasa Misailovic:
ViX: Analysis-driven Compiler for Efficient Low-Precision Variational Inference. 1-6 - Christian Lütkemeyer, Anton Belov:
Center-of-delay: a new metric to drive timing margin against spatial variation in complex SOCs. 1-6 - Hanna Müller, Nicky Zimmerman, Tommaso Polonelli, Michele Magno, Jens Behley
Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVs. 1-6 - Amro Eldebiky, Grace Li Zhang
Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test. 1-6 - Fabian Buschkowski
EasiMask-Towards Efficient, Automated, and Secure Implementation of Masking in Hardware. 1-6 - Hamza Errahmouni Barkam, Sanggeon Yun, Paul R. Genssler, Zhuowen Zou, Che-Kai Liu
HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable highly scaled FeFET. 1-6 - Ananda Samajdar, Jan Moritz Joseph, Tushar Krishna:
AIrchitect: Automating Hardware Architecture and Mapping Optimization. 1-6 - Kailash Prasad, Aditya Biswas, Arpita Kabra, Joycee Mekie:
PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM. 1-6
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