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José M. de la Rosa 0001
José Manuel de la Rosa 0001 – José Manuel de la Rosa Utrera
Person information
- affiliation (PhD 2000): University of Seville, IMSE-CNM, Spain
Other persons with the same name
- José M. de la Rosa — disambiguation page
- José Manuel de la Rosa-Vázquez
(aka: José Manuel de la Rosa 0002) — Instituto Politécnico Nacional, Mexico City, Mexico
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2020 – today
- 2024
- [j47]Manish Srivastava
A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing. IEEE Open J. Circuits Syst. 5: 42-54 (2024) - [j46]José M. de la Rosa
Incoming Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 1-4 (2024) - [j45]Javad Gorji
On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1082-1092 (2024) - [j44]Pablo Díaz-Lobo, Gustavo Liñán Cembrano
On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2006-2016 (2024) - [j43]Hampus Malmberg
A Control-Bounded Quadrature Leapfrog ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2483-2496 (2024) - [j42]Gustavo Liñán Cembrano
Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1677-1682 (2024) - [c91]Gustavo Liñán Cembrano
Live Demonstration: Automated Design of Analog and Mixed-Signal Circuits Using Neural Networks. ISCAS 2024: 1 - [c90]Gustavo Liñán Cembrano
Live Demonstration: Using ANNs to Predict the Evolution of Spectrum Occupancy. ISCAS 2024: 1 - [c89]A. Rojas
Deep Learning-Based Architecture for RF Frame Detection for CR Applications Using Spectrograms. MWSCAS 2024: 122-125 - 2023
- [j41]Nima Shahpari
A 12-Bit Low-Input Capacitance SAR ADC With a Rail-to-Rail Comparator. IEEE Access 11: 67113-67125 (2023) - [j40]Luis A. Camuñas-Mesa
Combining Software-Defined Radio Learning Modules and Neural Networks for Teaching Communication Systems Courses. Inf. 14(11): 599 (2023) - [j39]Promise I. Enwere, Encarnación Cervantes-Requena, Luis A. Camuñas-Mesa, José M. de la Rosa:
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems. Integr. 93: 102070 (2023) - [j38]Fatemeh Karami Horestani
Ultra-High-Resistance Pseudo-Resistors With Small Variations in a Wide Symmetrical Input Voltage Swing. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2794-2798 (2023) - [c88]Pablo Díaz-Lobo, José M. de la Rosa:
High-Level Design of Sigma-Delta Modulators using Artificial Neural Networks. ISCAS 2023: 1-5 - [c87]Javad Gorji
Bandpass $\Delta \Sigma$ Modulators with FIR Feedback. ISCAS 2023: 1-5 - [c86]Gordana Jovanovic-Dolecek, José M. de la Rosa:
Design of Wideband Multiplierless Compensators for Sharpened CIC Filters. MWSCAS 2023: 55-58 - [c85]Pablo Cruz-Dato, Miguel Chanca-Martín, José M. de la Rosa:
Design of a 15-Bit 160-MS/s Sigma-Delta DAC for BIST Generation in Automotive RADAR Systems. MWSCAS 2023: 365-369 - [c84]Hampus Malmberg, Fredrik Feyling, José M. de la Rosa:
Quadrature Control-Bounded ADCs. MWSCAS 2023: 380-384 - 2022
- [j37]José M. de la Rosa:
AI-Assisted Sigma-Delta Converters - Application to Cognitive Radio. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2557-2563 (2022) - [c83]Promise I. Okorie, Luis A. Camuñas-Mesa, José M. de la Rosa:
Using ANNs to Predict Frequency Spectrum Occupancy in Cognitive-Radio Receivers. DCIS 2022: 1-5 - [c82]Nima Shahpari
A Low-Input Capacitance 12-bit SAR ADC for use in Self-Powered IoT Nodes. ISCAS 2022: 2640-2644 - [c81]José M. de la Rosa:
Automated Design of Sigma-Delta Converters: From Know-How to AI-assisted Optimization. MWSCAS 2022: 1-3 - [i3]Hampus Malmberg, Fredrik Feyling, José M. de la Rosa:
Quadrature Control-Bounded ADCs. CoRR abs/2211.06745 (2022) - 2021
- [j36]Charanraj Mohan
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration. IEEE Access 9: 38043-38061 (2021) - [j35]José M. de la Rosa:
Editorial: A Year Ahead Full of New Initiatives. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 4 (2021) - [j34]José M. de la Rosa
Outgoing Editorial. IEEE Trans. Circuits Syst. II Express Briefs 68(12): 3477 (2021) - [c80]Hassan Aboushady, Alhassan Sayed, Luis A. Camuñas-Mesa, José M. de la Rosa:
Cognitive Radio Circuits and Systems - Application to Digitizers. ISCAS 2021: 1-5 - [c79]C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices. ISCAS 2021: 1-5 - [c78]Gordana Jovanovic-Dolecek
Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors. LASCAS 2021: 1-4 - [i2]C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices. CoRR abs/2103.01271 (2021) - [i1]Charanraj Mohan, Luis A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar. CoRR abs/2103.02651 (2021) - 2020
- [j33]José M. de la Rosa
Incoming Editorial. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 1-3 (2020) - [j32]Mohammad Honarparvar, José M. de la Rosa
A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-Based CT MASH ΔΣ Modulator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1519-1523 (2020) - [j31]Javad Ahmadi-Farsani
Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs. IEEE Trans. Circuits Syst. 67-I(10): 3297-3308 (2020) - [c77]Virginia Zúñiga-González
Using Neural Networks for Optimum band selection in Cognitive-Radio Systems. ICECS 2020: 1-4 - [c76]Tobi Delbrück, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang
Lessons Learned the Hard Way. ISCAS 2020: 1-18 - [c75]Charanraj Mohan
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar. ISCAS 2020: 1-5 - [c74]Gordana Jovanovic-Dolecek
Low Order Wideband Multiplierless Comb Compensator. MWSCAS 2020: 162-165
2010 – 2019
- 2019
- [j30]José M. de la Rosa
Guest Editorial Special Issue on the 2019 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 717 (2019) - [j29]José M. de la Rosa
Guest Editorial Special Issue on the 2019 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1607 (2019) - [c73]Javad Ahmadi-Farsani, José M. de la Rosa:
Bulk-Input VCO-Based Sigma-Delta ADCs with Enhanced Linearity in 28-nm FD-SOI CMOS. ISCAS 2019: 1-5 - [c72]Charanraj Mohan
A Current Attenuator for Efficient Memristive Crossbars Read-Out. ISCAS 2019: 1-5 - [c71]Javad Ahmadi-Farsani, José M. de la Rosa:
Analysis of Linearity in FD-SOI Body-Input Voltage Controlled Ring Oscillators - Application to ADCs. MWSCAS 2019: 1033-1036 - 2018
- [j28]José M. de la Rosa
Guest Editorial Special Issue on the 2018 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 531 (2018) - [j27]Beatriz Cortes-Delgadillo, Pablo A. Rodriguez-Navas, Luis I. Guerrero-Linares, José M. de la Rosa
Embedding MATLAB Optimizers in SIMSIDES for the High-Level Design of ΣΔ Modulators. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 547-551 (2018) - [j26]José M. de la Rosa
Guest Editorial Special Issue on the 2018 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1289 (2018) - [j25]Sohail Asghar
A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3628-3638 (2018) - [j24]Mohammad Honarparvar, José M. de la Rosa
A 0.9-V 100-µW Feedforward Adder-Less Inverter-Based MASH ΔΣ Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3675-3687 (2018) - [c70]Johannes Wagner, Maurits Ortmanns, José M. de la Rosa:
Man or Machine - Design Automation of Delta-Sigma Modulators. ISCAS 2018: 1-5 - [c69]Mohammad Honarparvar, José M. de la Rosa, Frederic Nabki, Mohamad Sawan:
Design Considerations of MASH ΔΣ Modulators with GRO-based Quantization. ISCAS 2018: 1-5 - [c68]Gerardo Molina Salgado
Behavioral Modeling of SAR ADCs in Simulink. ISCAS 2018: 1-5 - [c67]Sohail Asghar, Sohaib Saadat Afridi, Anu Pillai, Anita Schuler, José M. de la Rosa, Ivan John O'Connell
A 2MS/s, 11.22 ENOB, 3.2 Vpp-d SAR ADC with improved DNL and offset calculation. ISCAS 2018: 4- - 2017
- [j23]Gordana Jovanovic-Dolecek
Novel Multiplierless Wideband Comb Compensator with High Compensation Capability. Circuits Syst. Signal Process. 36(5): 2031-2049 (2017) - [c66]José M. de la Rosa
Emerging sigma-delta modulation techniques for an efficient digitization in the Internet of Things. MIXDES 2017: 15-16 - [c65]Mohammad Honarparvar, José M. de la Rosa
Novel band-pass ΔΣ modulators based on a modified adder-less feed-forward structure. MWSCAS 2017: 1288-1291 - 2016
- [c64]Alonso Morgado, Rocío del Río Fernández, José M. de la Rosa:
Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR. ISCAS 2016: 53-56 - [c63]Manuel Velasco-Jimenez, Rafael Castro-López
Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms. ISCAS 2016: 1438 - [c62]Manuel Velasco-Jimenez, Rafael Castro-López
High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms. ISCAS 2016: 1494-1497 - [c61]Gerard Fernandez, David Gascon
Design of a 9-bit 4MS/s wilkinson ADC for SiPM-based imaging detectors. MWSCAS 2016: 1-4 - 2015
- [j22]José M. de la Rosa
Guest Editorial: Next-Generation Delta-Sigma Converters. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(4): 481-483 (2015) - [j21]José M. de la Rosa
Next-Generation Delta-Sigma Converters: Trends and Perspectives. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(4): 484-499 (2015) - [j20]José M. de la Rosa
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014). IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 1897-1898 (2015) - [j19]Alejandro Garzón-Camacho
A Fast Readout Electronic System for Accurate Spatial Detection in Ion Beam Tracking for the Next Generation of Particle Accelerators. IEEE Trans. Instrum. Meas. 64(2): 318-327 (2015) - [c60]Teresa Serrano-Gotarredona, José M. de la Rosa:
Introduction to the IEEE-CASS workshop on micro/nanoelectronic circuits and systems. EUROCON 2015: 1 - [c59]Manuel Porcel de Soto, José M. de la Rosa
Simulation-based comparison of CNT-FETs and G-FETs from a circuit designer's perspective. ISCAS 2015: 105-108 - [c58]Alonso Morgado, Rocío del Río, José M. de la Rosa:
Energy efficient transconductor for widely programmable analog circuits and systems. ISCAS 2015: 1814-1817 - [c57]Saul Rodriguez
Overview of carbon-based circuits and systems. ISCAS 2015: 2912-2915 - [c56]Gerardo Molina Salgado
Novel two-stage comb decimator with improved frequency characteristic. LASCAS 2015: 1-4 - [c55]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators. MWSCAS 2015: 1-4 - 2014
- [j18]J. Gerardo García-Sánchez, José M. de la Rosa:
Efficient hybrid continuous-time/discrete-time cascade ΣΔ modulators for wideband applications. Microelectron. J. 45(10): 1234-1246 (2014) - [j17]Gerardo Molina Salgado, Alonso Morgado, Gordana Jovanovic-Dolecek
LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1442-1455 (2014) - [j16]José M. de la Rosa
Guest Editorial - Special Section on the 2013 IEEE Custom Integrated Circuits Conference (CICC 2013). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2217-2218 (2014) - [c54]José M. de la Rosa
Live demonstration: Using SIMULINK S-functions for the efficient modeling and simulation of analog integrated circuits and systems. ISCAS 2014: 437 - [c53]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
Design considerations of bandpass CT ΣΔ modulators for software-defined-radio receivers. ISCAS 2014: 718-721 - [c52]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
An overview of decimator structures for efficient sigma-delta converters: Trends, design issues and practical solutions. ISCAS 2014: 1592-1595 - [c51]J. G. Garcia-Sanchez, Daniel Calderón-Preciado, F. Sandoval-Ibarra, José M. de la Rosa
Behavioral modelling of a 4th order LP ΣΔ modulator-towards the design of a hybrid proposal. LASCAS 2014: 1-4 - [c50]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
Modified comb decimator for high power-of-two decimation factors. LASCAS 2014: 1-4 - [c49]Alejandro Garzón-Camacho
Readout electronic system for particle tracking in secondary electron detectors. MWSCAS 2014: 93-96 - [c48]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
Comb structures for Sigma-Delta ADCs with high even decimation factors. MWSCAS 2014: 583-586 - 2013
- [j15]Alejandro Garzón-Camacho
Design and experimental results of a preamplifier for particles tracking in secondary electron detectors. Microelectron. J. 44(10): 948-952 (2013) - [c47]José M. de la Rosa
An empirical and statistical comparison of state-of-the-art sigma-delta modulators. ISCAS 2013: 825-828 - [c46]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors. ISCAS 2013: 1260-1263 - [c45]Sohail Asghar, Rocío del Río
Undersampling RF-to-digital CT ΣΔ modulator with tunable notch frequency and simplified raised-cosine FIR feedback DAC. ISCAS 2013: 1994-1997 - [c44]Gerardo Molina Salgado, Gordana Jovanovic-Dolecek
Band-pass continuous-time ΣΔ modulators with widely tunable notch frequency for efficient RF-to-digital conversion. MWSCAS 2013: 566-569 - 2012
- [j14]José M. Dores, Edwin C. Becerra-Alvarez, Miguel A. Martins, José M. de la Rosa, Jorge R. Fernandes
Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback. Microelectron. J. 43(10): 714-720 (2012) - [j13]J. Gerardo García-Sánchez, José M. de la Rosa:
Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 285-294 (2012) - [j12]Alonso Morgado
High-Efficiency Cascade ΣΔ Modulators for the Next Generation Software-Defined-Radio Mobile Systems. IEEE Trans. Instrum. Meas. 61(11): 2860-2869 (2012) - [c43]José M. de la Rosa
Using behavioral modeling and simulation for learning communication circuits and systems. EDUCON 2012: 1-7 - [c42]José M. de la Rosa
Using nanoHUB.org for teaching and learning nanoelectronic devices in materials engineering. EDUCON 2012: 1-4 - [c41]José M. de la Rosa
A teamwork-based education strategy for teaching lab of analog integrated circuits design. EDUCON 2012: 1-4 - [c40]J. Gerardo García-Sánchez, José M. de la Rosa:
Efficient Hybrid Continuous-Time/Discrete-Time ∑ Δ Modulators for Broadband Wireless Telecom Systems. DoCEIS 2012: 485-492 - [c39]Alonso Morgado
A power-scalable concurrent cascade 2-2-2 SC ΣΔ modulator for Software Defined Radio. ISCAS 2012: 516-519 - [c38]Alejandro Garzón-Camacho
A preamplifier for the front-end readout system of particles tracking in secondary electron detectors. ISCAS 2012: 1171-1174 - [c37]José M. de la Rosa
Behavioral modeling techniques for teaching communication circuits and systems. ISCAS 2012: 2453-2456 - [c36]Nader Rafla, Mohamad Sawan, José M. de la Rosa
Welcome to the 55th IEEE international midwest symposium on circuits and systems (MWSCAS 2012). MWSCAS 2012: 1 - [c35]J. Gerardo García-Sánchez, José M. de la Rosa
Hybrid continuous-time/discrete-time circuit techniques for the efficient implementation of wideband ΣΔ ADCs. MWSCAS 2012: 374-377 - [c34]Sohail Asghar, Rocío del Río
A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW flexible 4th-order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS. VLSI-SoC 2012: 47-52 - 2011
- [j11]José M. de la Rosa:
Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 1-21 (2011) - [c33]Edwin C. Becerra-Alvarez, José M. de la Rosa, Federico Sandoval-Ibarra:
Design considerations and experimental results of continuously-tuned reconfigurable CMOS LNAs. ISCAS 2011: 273-276 - [c32]J. Gerardo García-Sánchez, José M. de la Rosa:
Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom. VLSI-SoC (Selected Papers) 2011: 124-143 - [c31]J. Gerardo García-Sánchez, José M. de la Rosa:
Multirate hybrid continuous-time/discrete-time cascade 2-2 ΣΔ modulator for wideband telecom. VLSI-SoC 2011: 314-318 - 2010
- [j10]Alonso Morgado
A 0.13 µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications. Microelectron. J. 41(5): 277-290 (2010) - [c30]Alonso Morgado
A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. ESSCIRC 2010: 418-421 - [c29]J. Gerardo García-Sánchez, José M. de la Rosa:
Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages. ISCAS 2010: 33-36
2000 – 2009
- 2009
- [j9]José M. de la Rosa, Rafael Castro-López
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey. Microelectron. J. 40(1): 156-176 (2009) - [c28]Alonso Morgado
A flexible resonation-based cascade ΣΔ modulator with simplified cancellation logic. ICECS 2009: 755-758 - [c27]Edwin C. Becerra-Alvarez, Federico Sandoval-Ibarra, José M. de la Rosa:
Adaptive CMOS LNAs for Beyond-3G RF Receivers - A Multi-standard GSM/WCDMA/BT/WLAN Case Study. ISCAS 2009: 417-420 - [c26]José M. de la Rosa, Alonso Morgado
Hybrid Continuous-Time/Discrete-Time Cascade SigmaDelta Modulators with Programmable Resonation. ISCAS 2009: 2249-2252 - 2008
- [j8]Alonso Morgado
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK. Integr. 41(2): 269-280 (2008) - [j7]Ramon Tortosa Navas, José M. de la Rosa, Francisco V. Fernández
Clock jitter error in multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform. Microelectron. J. 39(1): 137-151 (2008) - [c25]Alonso Morgado
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications. DATE 2008: 862-867 - 2007
- [c24]Alonso Morgado
Novel topologies of cascade ΣΔ modulators for low-voltage wideband applications. ECCTD 2007: 136-139 - [c23]Ramon Tortosa Navas, Antonio Aceituno, José M. de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator. ISCAS 2007: 1-4 - [c22]Alonso Morgado, Rocío del Río, José M. de la Rosa:
Design of a 130-nm CMOS Reconfigurable Cascade Sigma Delta Modulator for GSM/UMTS/Bluetooth. ISCAS 2007: 725-728 - [c21]Alonso Morgado, Rocío del Río, José M. de la Rosa:
A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio Receivers. ISCAS 2007: 2950-2953 - 2006
- [j6]Ramon Tortosa Navas, José M. de la Rosa, Francisco V. Fernández
A New High-Level Synthesis Methodology of Cascaded Continuous-Time Sigma Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 739-743 (2006) - [c20]Jesús Ruiz-Amaya, Manuel Delgado-Restituto
A 12-bit CMOS Current Steering D/A Converter for Embedded Systems. APCCAS 2006: 1671-1674 - [c19]Alonso Morgado, Rocío del Río, José M. de la Rosa, Fernando Medeiro, Maria Belen Pérez-Verdú, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
Reconfiguration of cascade Sigma Delta modulators for multistandard GSM/Bluetooth/UMTS/WLAN transceivers. ISCAS 2006 - [c18]Ramon Tortosa Navas, José M. de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández:
Design of a 1.2-V cascade continuous-time Delta Sigma modulator for broadband telecommunications. ISCAS 2006 - [c17]Ramon Tortosa Navas, Antonio Aceituno, José M. de la Rosa, Francisco V. Fernández
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator. VLSI-SoC 2006: 267-271 - 2005
- [j5]José M. de la Rosa, Sara Escalera, Belén Pérez-Verdú
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs. IEEE J. Solid State Circuits 40(11): 2246-2264 (2005) - [j4]Jesús Ruiz-Amaya, José M. de la Rosa, Francisco V. Fernández
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(9): 1795-1810 (2005) - [c16]Ramon Tortosa Navas, José M. de la Rosa, Ángel Rodríguez-Vázquez
Analysis of clock jitter error in multibit continuous-time ΣΔ modulators with NRZ feedback waveform. ISCAS (4) 2005: 3103-3106 - [c15]Manuel Delgado-Restituto
An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology. ISCAS (5) 2005: 4626-4629 - [c14]Ramon Tortosa Navas, José M. de la Rosa, Ángel Rodríguez-Vázquez
A direct synthesis method of cascaded continuous-time sigma-delta modulators. ISCAS (6) 2005: 5585-5588 - [c13]Jesús Ruiz-Amaya, José M. de la Rosa, Manuel Delgado-Restituto
Behavioral modeling simulation and high-level synthesis of pipeline A/D converters. ISCAS (6) 2005: 5609-5612 - 2004
- [j3]Rocío del Río
Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 47-62 (2004) - [c12]Jesús Ruiz-Amaya, José M. de la Rosa, Fernando Medeiro, Francisco V. Fernández, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment. ISCAS (5) 2004: 97-100 - [c11]José M. García-González, Sara Escalera, José M. de la Rosa, Oscar Guerra, Fernando Medeiro, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
A 0.35µm CMOS 17-bit@40kS/s sensor A/D interface based on a programmable-gain cascade 2-1 Sigma Delta modulator. ISCAS (1) 2004: 205-208 - [c10]Sara Escalera, José M. García-González, Oscar Guerra, José M. de la Rosa, Fernando Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
An alternative DFT methodology to test high-resolution Sigma Delta modulators. ISCAS (1) 2004: 257-260 - 2003
- [c9]Rafael Castro-López, José M. de la Rosa, R. Romay, Rocío del Río, Fernando Medeiro, Francisco V. Fernández:
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey. FDL 2003: 121-133 - [c8]Fernando Medeiro, José M. de la Rosa, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
Design considerations for an automotive sensor interface Sigma-Delta modulator. ISCAS (3) 2003: 538-541 - [c7]J. Moreno-Reina, José M. de la Rosa, Fernando Medeiro, R. Romay, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time Sigma-Delta modulators. ISCAS (4) 2003: 620-623 - 2002
- [c6]Rocío del Río, Fernando Medeiro, José M. de la Rosa, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
A 2.5-V Sigma-Delta modulator in 0.25-µm CMOS for ADSL. ISCAS (3) 2002: 301-304 - 2001
- [c5]Rocío del Río, José M. de la Rosa, Fernando Medeiro, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez:
A High-performance sigma-delta ADC for ADSL applications in 0.35 μm CMOS digital technology. ICECS 2001: 501-504 - [c4]José M. de la Rosa, Maria Belen Pérez-Verdú, Fernando Medeiro, Rocío del Río, Ángel Rodríguez-Vázquez:
Effect of non-linear settling error on the harmonic distortion of fully-differential switched-current bandpass Sigma-Delta modulators. ISCAS (1) 2001: 340-343 - [c3]José M. de la Rosa, Maria Belen Pérez-Verdú
Analysis and experimental characterization of idle tones in 2nd-order bandpass Sigma-Delta modulators-a 0.8 um CMOS switched-current case study. ISCAS (4) 2001: 774-777 - 2000
- [j2]José M. de la Rosa
A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion. IEEE J. Solid State Circuits 35(8): 1220-1226 (2000)
1990 – 1999
- 1999
- [c2]José M. de la Rosa, Maria Belen Pérez-Verdú, Rocío del Río, Ángel Rodríguez-Vázquez:
Non-ideal quantization noise shaping in switched-current bandpass Sigma-Delta modulators. ISCAS (2) 1999: 476-479 - 1998
- [c1]José M. de la Rosa, Andreas Kaiser
Interactive verification of switched-current sigma-delta modulators. ICECS 1998: 157-160 - 1997
- [j1]Fernando Medeiro, Belén Pérez-Verdú, José M. de la Rosa, Ángel Rodríguez-Vázquez:
Using CAD tools for shortening the design cycle of high-performance sigma-delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology. Int. J. Circuit Theory Appl. 25(5): 319-334 (1997)
Coauthor Index
Francisco V. Fernández 0001
aka: Francisco Vidal Fernández Fernández
aka: Francisco Vidal Fernández Fernández
Rocío del Río Fernández
aka: Rocío del Río
aka: Rocío del Río
Maria Belen Pérez-Verdú
aka: Belén Pérez-Verdú
aka: Belén Pérez-Verdú
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