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32nd FCCM 2024: Orlando, FL, USA
- 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2024, Orlando, FL, USA, May 5-8, 2024. IEEE 2024, ISBN 979-8-3503-7243-4
- Qin Luo
, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F. Y. Young, Martin D. F. Wong:
A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. 1-7 - Dehao Xiang, Chenyang Li, Wenjin Huang, Yihua Huang:
A Novel FPGA Accelerator of R(2+1)D. 1-7 - Qianyu Cheng, Teng Wang, Chao Wang:
Ph.D. Project: Optimizing the Data Traffic for Large Graph Processing on FPGA via a Stateful Approach. 1-2 - Zhihan Xu, Yang Yang, Rajgopal Kannan, Viktor K. Prasanna:
Bandwidth Efficient Homomorphic Encrypted Discrete Fourier Transform Acceleration on FPGA. 1-12 - Mohamed W. Hassan, Hatem Ltaief, Suhaib A. Fahmy:
High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs. 13-23 - Shuang Liang, Yuncheng Lu, Ce Guo, Wayne Luk, Paul H. J. Kelly:
PCQ: Parallel Compact Quantum Circuit Simulation. 24-31 - Abdul Rehman Tareen, Marius Meyer, Christian Plessl, Tobias Kenter:
HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. 32-42 - Sergey Gribok, Bogdan Pasca:
Efficient 8-bit Matrix Multiplication on Intel Agilex-5 FPGAs. 43-53 - Endri Taka, Dimitrios Gourounas, Andreas Gerstlauer, Diana Marculescu, Aman Arora
Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs. 54-65 - Bingyi Zhang, Rajgopal Kannan, Carl E. Busart, Viktor K. Prasanna:
GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA. 66-77 - Dhruv Parikh, Shouyi Li, Bingyi Zhang, Rajgopal Kannan, Carl E. Busart, Viktor K. Prasanna:
Accelerating ViT Inference on FPGA through Static and Dynamic Pruning. 78-89 - Shuxin Yang, Chenchen Ding, Mingqiang Huang, Kai Li, Chenghao Li, Zikun Wei, Sixiao Huang, Jingyao Dong, Liuyang Zhang, Hao Yu:
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. 90-96 - Tomás Martínek, Jan Korenek, Tomás Cejka:
LGBM2VHDL: Mapping of LightGBM Models to FPGA. 97-103 - Rishov Sarkar, Rachel Paul, Cong Hao:
LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization. 104-114 - Zhili Xiong, Rachel Selina Rajarathnam, David Z. Pan:
A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs. 115-125 - Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser:
Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. 126-132 - Mohamed Shahawy, Canberk Sönmez, Cemalettin Belentepe, Paolo Ienne:
HardCilk: Cilk-like Task Parallelism for FPGAs. 140-150 - Rami Beidas, Jason Helge Anderson:
Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams. 151-161 - Jinwoo Choi, Yeonan Ha, Hanna Cha, Seil Lee, Sungchul Lee, Jounghoo Lee, Shinhaeng Kang, Bongjun Kim
MPC-Wrapper: Fully Harnessing the Potential of Samsung Aquabolt-XL HBM2-PIM on FPGAs. 162-172 - Nikolaos Kyparissas
FINESSD: Near-Storage Feature Selection with Mutual Information for Resource-Limited FPGAs. 173-184 - Petros Toupas, Zhewen Yu, Christos-Savvas Bouganis, Dimitrios Tzovaras:
SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction. 185-196 - Wenlu Peng, Jianjun Chen, Wenjin Huang, Yihua Huang:
MRH-GCN: An Efficient GCN Accelerator for Multi-Relation Heterogeneous Graph. 197-203 - Peter Mbua, Zhaoqi Wang, Maximillian Panoff, Christophe Bobda:
A Near-Sensor Image Processing Accelerator for Low-end FPGA Design. 211 - Shahzad Ahmad Butt, Benjamin Reynolds, Veeraraghavan Ramamurthy, Xiao Xiao, Pohrong Chu, Setareh Sharifian, Sergey Gribok, Bogdan Pasca:
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs. 212 - Xilai Dai, Yuzong Chen, Mohamed S. Abdelfattah:
FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. 213 - Hao Zhou, Yang Liu
SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design. 214 - Geetesh More, Suprio Ray, Kenneth B. Kent:
Learned Index Acceleration with FPGAs: A SMART Approach. 215 - Xiangzhi Xu, Qi Liu, Wenjin Huang, Wenlu Peng, Yihua Huang:
SpGCN: An FPGA-Based Graph Convolutional Network Accelerator for Sparse Graphs. 216 - Hassan Nassar, Lars Bauer, Jörg Henkel:
HBMorphic: FHE Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA. 217 - Scott Smith, Yuan Ma, Marissa Lanz, Bill Dai, Martin Ohmacht, Bharat Sukhwani, Hubertus Franke, Volodymyr V. Kindratenko, Deming Chen:
OS4C: An Open-Source SR-IOV System for SmartNIC-based Cloud Platforms. 218 - Hanning Chen, Ali Zakeri, Yang Ni, Fei Wen, Behnam Khaleghi, Hugo Latapie, Mohsen Imani:
High-Performance Reconfigurable Accelerator for Knowledge Graph Reasoning. 219 - Yuhao Liu
BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators. 220 - Huawen Liang, Qizhe Wu, Wei Yuan, Teng Tian, Xi Jin:
RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA. 221 - Taikun Zhang, Andrew Boutros, Sergey Gribok, Kwadwo Boateng, Vaughn Betz:
Stay Flexible: A High-Performance FPGA NPU Overlay for Graph Neural Networks. 222 - M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews:
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators. 223 - Stephanie Soldavini, Felix Suchert, Serena Curzel, Michele Fiorito, Karl F. A. Friebel, Fabrizio Ferrandi, Radim Cmar, Jerónimo Castrillón, Christian Pilato:
Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes. 224 - Dipal Halder, Sandip Ray:
PhD Project: Reconfigurable Network on Chip Architecture Through Topology Obfuscation For Protecting SoC Against Reverse Engineering. 227-228 - Ryota Miyagi, Hideki Takase:
Ph.D. Project: Field-Programmable Computing for Bayesian Network Structure Learning. 229-230 - Zhendong Zheng, Teng Wang, Chao Wang:
Ph.D. Project: Achieving Low-Latency Acceleration on Multi-FPGA for GPT Application. 231-232 - James Bickerstaff, Alan D. George:
Ph.D. Project: Investigating oneAPI Performance & Scalability using Feedforward FFT Architectures. 233-234 - Daniel C. Stumpp, Alan D. George:
Ph.D. Project: Accelerated Machine Learning for On-Orbit OPIR Target Detection. 235-236 - Tendayi Kamucheka, David Andrews:
Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators. 237-238 - Bardia Babaei, Dirk Koch:
Ph.D. Project: ManAge: A Tool for Timing Characterization of FPGAs. 239-240 - Patrick Schmidt, Jürgen Becker:
Ph.D. Project: Compiler-Driven Hardware/Software Co- Design for Embedded AI. 241-242 - Peter Mbua, Christophe Bobda:
Ph.D. Project Investigating Chiplet Interfaces for Efficient Near-Sensor Computing in Visual On-Device Intelligence. 243-244 - Rishov Sarkar, Cong Hao:
Ph.D. Project: Modernizing High-Level Hardware Design Workflows. 245-246 - Muhammed Kawser Ahmed, Christophe Bobda:
Ph.D. Project - IsoFPGA - A Novel CMOS Galvanic Isolation for Remote Physical Attacks in Multi-tenant Cloud FPGA. 247-248 - Abigail N. Butka, Christophe Bobda:
Ph.D. Project: Systems-on-Chip to Implement Zero-Trust Architectures. 249-250
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