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14. ACM Great Lakes Symposium on VLSI 2004: Boston, MA, USA
- David Garrett, John C. Lach, Charles A. Zukowski:
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004. ACM 2004, ISBN 1-58113-853-9
General Session
- Xinmiao Zhang, Keshab K. Parhi
:
High-speed architectures for parallel long BCH encoders. 1-6 - Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili:
Optimal partitioning of globally asychronous locally synchronous processor arrays. 7-12
CAD
- Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
High level techniques for power-grid noise immunity. 13-18 - Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer:
TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. 19-24 - Qinwei Xu, Pinaki Mazumder:
Modeling of transmission lines with EM wave coupling by the finite difference quadrature method. 25-28 - Liang Zhang, Wentai Liu, Rizwan Bashirullah, John M. Wilson, Paul D. Franzon:
Simplified delay design guidelines for on-chip global interconnects. 29-32 - Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
Design and optimization of MOS current mode logic for parameter variations. 33-38
VLSI design
- Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin:
A 2 Gb/s balanced AES crypto-chip implementation. 39-44 - Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha:
Quality-of-service and error control techniques for network-on-chip architectures. 45-50 - Zhiyuan Yan, Dilip V. Sarwate:
Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithm. 51-56 - Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A compact DSP core with static floating-point unit & its microcode generation. 57-60 - Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell:
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. 61-66
CAD
- Alexey Lvov, Fook-Luen Heng:
A graph based simplex method for the integer minimum perturbation problem with sum and difference constraints. 67-72 - David W. Nellans, Vamshi Krishna Kadaru, Erik Brunvand:
ARCS: an architectural level communication driven simulator. 73-77 - Stergios Stergiou, Konstantinos Daskalakis, George K. Papakonstantinou:
A fast and efficient heuristic ESOP minimization algorithm. 78-81 - Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A memory aware behavioral synthesis tool for real-time VLSI circuits. 82-85
Testing
- Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba:
Low-power weighted pseudo-random BIST using special scan cells. 86-91 - Miroslav N. Velev
Efficient formal verification of pipelined processors with instruction queues. 92-95 - Hamidreza Hashempour, Fabrizio Lombardi:
Evaluation of heuristic techniques for test vector ordering. 96-99 - Franco Fummi, Graziano Pravadelli:
Logic-level analysis of high-level faults. 100-103
Poster Session 1
- Vijay Pillai, Harley Heinrich, K. V. S. Rao, Rene Martinez:
A stacked antenna broad-band RFID front-end for UHF and microwave bands. 104-108 - Debayan Bhaduri, Sandeep K. Shukla:
NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures. 109-112 - David A. Papa, Saurabh N. Adya, Igor L. Markov:
Constructive benchmarking for placement. 113-118 - Ali Bastani, Charles A. Zukowski:
Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. 119-122 - Jason W. Horihan, Yung-Hsiang Lu:
Improving FSM evolution with progressive fitness functions. 123-126 - Feng Shi, Yiorgos Makris
Fault simulation and random test generation for speed-independent circuits. 127-130 - Jia Wang, Hai Zhou:
Minimal period retiming under process variations. 131-135 - Marco Ottavi
Simulation of reconfigurable memory core yield. 136-140 - Jong-Ru Guo, Chao You, Peter F. Curran, Michael Chu, Kuan Zhou, Jiedong Diao, A. George, Russell P. Kraft, John F. McDonald:
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. 141-144 - Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham:
On-chip delay measurement for silicon debug. 145-148 - Yarallah Koolivand, Ali Zahabi, Nasser Masoumi:
Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique. 149-153 - Zhengyu Wang, M.-C. Frank Chang, Jessica Chiatai Chou:
A simple DDS architecture with highly efficient sine function lookup table. 154-157 - Amir Amirabadi
Leakage current reduction by new technique in standby mode. 158-161 - Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
Macro-models for high level area and power estimation on FPGAs. 162-165 - Keoncheol Shin, Taewhan Kim:
Leakage power minimization for the synthesis of parallel multiplier circuits. 166-169 - Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Ibrahim Kolcu:
Tuning data replication for improving behavior of MPSoC applications. 170-173 - Abdel Ejnioui, Abdelhalim Alsharqawi:
Self-resetting stage logic pipelines. 174-177 - Shaolei Quan, Chin-Long Wey:
A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors. 178-182 - Mohammad Moghaddam Tabrizi, Amir Amirabadi
A CMOS elliptic low-pass switched capacitor ladder filter for video communication using bilinear implementation. 183-186 - Sudarshan Banerjee, Nikil D. Dutt
FIFO power optimization for on-chip networks. 187-191 - Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. 192-195
CAD
- Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
A device-level placement with multi-directional convex clustering. 196-201 - Martin Paluszewski, Pawel Winter, Martin Zachariasen
A new paradigm for general architecture routing. 202-207 - Hasan Arslan, Shantanu Dutt:
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. 208-213 - Andrew B. Kahng, Igor L. Markov, Sherief Reda:
On legalization of row-based placements. 214-219 - Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. 220-223
Low Power
- Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson:
Mitigating static power in current-sensed interconnects. 224-229 - Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky:
Characterization of logic circuit techniques for high leakage CMOS technologies. 230-235 - Alberto Bocca, Sabino Salerno, Enrico Macii, Massimo Poncino:
Energy-efficient bus encoding for LCD displays. 240-243 - Yuantao Peng, Xun Liu:
Power macromodeling of global interconnects considering practical repeater insertion. 244-247
General Session
- Hiren D. Patel, Sandeep K. Shukla:
Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models. 248-253 - Shalini Ghosh, F. Joel Ferguson:
Estimating detection probability of interconnect opens using stuck-at tests. 254-259 - Roghoyeh Salmeh, Brent Maundy:
VLSI implementation of an automatic Q tuning system. 260-265
CAD
- Bhaskar Mukherjee, Lei Wang, Andrea Pacelli:
A practical approach to modeling skin effect in on-chip interconnects. 266-270 - Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. 271-276 - Guido Bertoni, Marco Macchetti, Luca Negri, Pasqualina Fragneto:
Power-efficient ASIC synthesis of cryptographic sboxes. 277-281 - Hayward H. Chan, Igor L. Markov:
Practical slicing and non-slicing block-packing without simulated annealing. 282-287 - Tun Li, Yang Guo, Sikun Li:
Assertion-based automated functional vectors generation using constraint logic programming. 288-291
VLSI circuits
- Chung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst:
Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. 292-297 - Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Design of a nanosensor array architecture. 298-303 - Edward K. S. Au, Wing-Hung Ki
A binary--search switched--current sensing scheme for 4-state MRAM. 304-307 - Adam O. Lee, Robert J. Weber:
Design of a 5-Gb/s PRBS generator in 0.18µm CMOS process. 308-311 - Manuel Salim Maza, Mónico Linares Aranda:
Analysis and verification of interconnected rings as clock distribution networks. 312-315
Testing
- Hongjoong Shin, Hak-soo Yu, Jacob A. Abraham:
LFSR-based BIST for analog circuits using slope detection. 316-321 - Chin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba:
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement. 322-327 - Ji Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham:
An efficient linearity test for on-chip high speed ADC and DAC using loop-back. 328-331
Future technologies
- Ramprasad Ravichandran, Nihal Ladiwala, Jean Nguyen, Michael T. Niemier, Sung Kyu Lim
Automatic cell placement for quantum-dot cellular automata. 332-337 - Shamik Das, Anantha P. Chandrakasan, Rafael Reif:
Timing, energy, and thermal performance of three-dimensional integrated circuits. 338-343 - Fengming Zhang, Rui Tang, Yong-Bin Kim:
SET-based nano-circuit simulation and design method using HSPICE. 344-347
Poster session 2
- Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi:
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. 348-353 - Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji:
CESC: a visual formalism for specification and verification of SoCs. 354-357 - Kenneth W. Batcher, Robert A. Walker:
Cluster miss prediction for instruction caches in embedded networking applications. 358-363 - Fadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell:
The design of the fixed point unit for the z990 microprocessor. 364-367 - Zhen Guo:
How to reduce aliasing in linear analog testing. 368-371 - Long Bu, John A. Chandy
A keyword match processor architecture using content addressable memory. 372-376 - Anh-Tuan Phan, Chang-Wan Kim, Min-Suk Kang, Sang-Gug Lee, Chun-Deok Su, Hoon-Tae Kim:
A high performance CMOS direct down conversion mixer for UWB system. 377-380 - M. Reza Samadi, Aydin I. Karsilayan
Multi-peak bandwidth enhancement technique for multistage amplifiers. 381-384 - Thomas Eschbach, Wolfgang Günther, Bernd Becker
Orthogonal hypergraph routing for improved visibility. 385-388 - Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas:
Low power ATPG for path delay faults. 389-392 - Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. 393-396 - David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. 397-400 - Kundan Nepal, Hui-Yuan Song, R. Iris Bahar
RESTA: a robust and extendable symbolic timing analysis tool. 407-412 - Mirko Loghi, Massimo Poncino, Luca Benini:
Cycle-accurate power analysis for multiprocessor systems-on-a-chip. 410-406 - Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver:
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. 413-416 - Costas Laoudias, Dimitris Nikolos:
A new test pattern generator for high defect coverage in a BIST environment. 417-420 - Luigi Dadda, Marco Macchetti, Jeff Owen:
An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512). 421-425 - Jing Huang, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation. 426-429 - Ozgur Celebican, Tajana Simunic Rosing, Vincent John Mooney III:
Energy estimation of peripheral devices in embedded systems. 430-435 - Luca Macchiarulo
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. 436-439
Low Power
- Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon:
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. 440-443 - Alok A. Katkar, James E. Stine:
Modified booth truncated multipliers. 444-447 - Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno:
Design methodology for semi custom processor cores. 448-452
VLSI design
- Nele Mentens, Siddika Berna Örs, Bart Preneel:
An FPGA implementation of an elliptic curve processor GF(2m). 454-457 - Miguel A. Melgarejo, Carlos Andrés Peña-Reyes:
Hardware architecture and FPGA implementation of a type-2 fuzzy system. 458-461 - Zhiyuan Yan, Dilip V. Sarwate:
High-speed systolic architectures for finite field inversion and division. 462-465
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