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ICCD 2013: Asheville, NC, USA
- 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-2987-0
- Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor:
Functional Fmax test-time reduction using novel DFTs for circuit initialization. 1-6 - César A. M. Marcon
, Alexandre M. Amory
Phoenix NoC: A distributed fault tolerant architecture. 7-12 - Maurice Peemen, Arnaud A. A. Setio, Bart Mesman, Henk Corporaal:
Memory-centric accelerator design for Convolutional Neural Networks. 13-19 - Yang Xiao, Chuanjun Zhang, Kevin Inck, Vijaykrishnan Narayanan:
Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems. 20-25 - Steven J. Battle, Mark Hempstead:
Characterizing the costs and benefits of hardware parallelism in accelerator cores. 26-32 - Chia-Hao Lin, Ing-Chao Lin:
High accuracy approximate multiplier with error correction. 33-38 - Armin Alaghi, John P. Hayes:
Exploiting correlation in stochastic circuit design. 39-46 - Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Statistical analysis and modeling for error composition in approximate computation circuits. 47-53 - Guangshuo Liu, Jinpyo Park, Diana Marculescu
Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems. 54-61 - Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra
Energy-aware synthesis of application specific MPSoCs. 62-69 - Jason M. Allred
Long term sustainability of differentially reliable systems in the dark silicon era. 70-77 - Yiding Han, Koushik Chakraborty, Sanghamitra Roy
A global router on GPU architecture. 78-84 - Farrukh Hijaz, Qingchuan Shi, Omer Khan:
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages. 85-92 - David Kadjo, Hyungjun Kim, Paul Gratz
Power gating with block migration in chip-multiprocessor last-level caches. 93-99 - Sparsh Mittal
FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration. 100-107 - Steven J. Battle, Mark Hempstead:
Register allocation and VDD-gating algorithms for out-of-order architectures. 108-114 - Youyou Lu, Jiwu Shu, Jia Guo, Shuai Li, Onur Mutlu:
LightTx: A lightweight transactional design in flash-based SSDs to support flexible transactions. 115-122 - Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. 123-130 - Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie:
Low power multi-level-cell resistive memory design with incomplete data mapping. 131-137 - Tao Zhang, Cong Xu, Yuan Xie, Guangyu Sun:
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system. 138-144 - Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia A. Lebedev, Srinivas Devadas:
Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine. 145-153 - Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis
Rationale for a 3D heterogeneous multi-core processor. 154-168 - Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou:
Accelerator-rich CMPs: From concept to real hardware. 169-176 - Licheng Chen, Yanan Wang, Zehan Cui, Yongbing Huang, Yungang Bao, Mingyu Chen:
Scattered superpage: A case for bridging the gap between superpage and page coloring. 177-184 - Mushfique Junayed Khurshid, Mikko H. Lipasti:
Data compression for thermal mitigation in the Hybrid Memory Cube. 185-192 - Milan Pavlovic, Nikola Puzovic, Alex Ramírez:
Data placement in HPC architectures with heterogeneous off-chip memory. 193-200 - Vikram B. Suresh, Sandip Kundu:
Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array. 201-206 - Nikos Foutris, Dimitris Gizopoulos, John Kalamatianos, Vilas Sridharan:
Assessing the impact of hard faults in performance components of modern microprocessors. 207-214 - Sachhidh Kannan, Ramesh Karri
Sneak path testing and fault modeling for multilevel memristor-based memories. 215-220 - Dawei Li, Ji-Hoon Kim, Seda Ogrenci Memik:
Integrating thermocouple sensors into 3D ICs. 221-226 - Prasanjeet Das, Sandeep K. Gupta:
Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. 227-234 - Pey-Chang Kent Lin, Sunil P. Khatri:
Noise-based algorithms for functional equivalence and tautology checking. 235-240 - Kuan Fang, Yufei Ni, Jiayuan He, Zonghui Li, Shuai Mu, Yangdong Deng:
FastLanes: An FPGA accelerated GPU microarchitecture simulator. 241-248 - Guohong Li, Zhenyu Liu, Sanchuan Guo, Chongmin Li, Dongsheng Wang:
Bayesian theory oriented Optimal Data-Provider Selection for CMP. 249-256 - Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
Selected inversion for vectorless power grid verification by exploiting locality. 257-263 - Travis Boraten, Avinash Karanth Kodi:
Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures. 264-271 - Julio Villalba
Efficient floating-point representation for balanced codes for FPGA devices. 272-277 - Long Chen, Yanan Cao, Zhao Zhang:
Free ECC: An efficient error protection for compressed last-level caches. 278-285 - Arkaprava Basu, Derek Hower, Mark D. Hill, Michael M. Swift:
FreshCache: Statically and dynamically exploiting dataless ways. 286-293 - Karthik T. Sundararajan, Timothy M. Jones
RECAP: Region-Aware Cache Partitioning. 294-301 - Alen Bardizbanyan, Magnus Själander
Speculative tag access for reduced energy dissipation in set-associative L1 data caches. 302-308 - Alberto A. Del Barrio
Exploring the energy efficiency of Multispeculative Adders. 309-315 - Nathaniel A. Conos, Miodrag Potkonjak:
A temperature-aware synthesis approach for simultaneous delay and leakage optimization. 316-321 - Infall Syafalni
A TCAM generator for packet classification. 322-328 - Matheus Trevisan Moreira, Ney Laert Vilar Calazans
Voltage scaling on C-elements: A speed, power and energy efficiency analysis. 329-334 - Jie Chen, Fan Yao
Watts-inside: A hardware-software cooperative approach for Multicore Power Debugging. 335-342 - Jan Hoogerbrugge:
Variation tolerance and error resilience in a low power wireless receiver. 343-348 - Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. 349-356 - Gert-Jan van den Braak, Juan Gómez-Luna
Simulation and architecture improvements of atomic operations on GPU scratchpad memory. 357-362 - Tosiron Adegbija, Ann Gordon-Ross:
Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems. 363-368 - Qingchuan Shi, Farrukh Hijaz, Omer Khan:
Towards efficient dynamic data placement in NoC-based multicores. 369-376 - Bhawna Nayak, John Jose
SLIDER: Smart Late Injection DEflection Router for mesh NoCs. 377-383 - Kamran Rahmani, Prabhat Mishra
Scalable trace signal selection using machine learning. 384-389 - Mahmoud Elbayoumi
Selecting critical implications with set-covering formulation for SAT-based Bounded Model Checking. 390-395 - Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer
Equivalence checking of partial designs using dependency quantified Boolean formulae. 396-403 - Héctor J. García, Igor L. Markov:
Quipu: High-performance simulation of quantum circuits using stabilizer frames. 404-410 - Muhammad Ahsan
Performance simulator based on hardware resources constraints for ion trap quantum computer. 411-418 - Martin Suchara
QuRE: The Quantum Resource Estimator toolbox. 419-426 - Xiao Liu, John Kubiatowicz:
Chisel-Q: Designing quantum circuits with a scala embedded language. 427-434 - Ankur Sharma, Joseph Sloan, Lucas Francisco Wanner
Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware. 435-438 - Yijie Huangfu, Wei Zhang:
Compiler-based approach to reducing leakage energy of instruction scratch-pad memories. 439-442 - Övünç Kocabas, Tolga Soyata
Assessment of cloud-based health monitoring using Homomorphic Encryption. 443-446 - Qing Xie, Tiansong Cui, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
Semi-analytical current source modeling of near-threshold operating logic cells considering process variations. 447-450 - Madhushika M. E. Karunarathna, Yu-Chu Tian
Algorithm clustering for multi-algorithm processor design. 451-454 - Letian Yi, Jiwu Shu, Jiaxin Ou, Weimin Zheng:
CG-Resync: Conversion-guided resynchronization for a SSD-based RAID array. 455-458 - Seongbo Shim, Minyoung Mo, Sangmin Kim, Youngsoo Shin:
Analysis and minimization of short-circuit current in mesh clock network. 459-462 - Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran:
LPScan: An algorithm for supply scaling and switching activity minimization during test. 463-466 - Fan Yao
JOP-alarm: Detecting jump-oriented programming-based anomalies in applications. 467-470 - Hassan Salmani, Mohammad Tehranipoor, Ramesh Karri
On design vulnerability analysis and trust benchmarks development. 471-474 - Silvia Lovergine, Fabrizio Ferrandi
Dynamic AC-scheduling for hardware cores with unknown and uncertain information. 475-478 - Ying Teng, Baris Taskin:
Resonant frequency divider design methodology for dynamic frequency scaling. 479-482 - Gongming Yang, Hao He, Jiang Hu:
Resource allocation algorithms for guaranteed service in application-specific NoCs. 483-486 - Ayan Mandal, Kalyana C. Bollapalli, Nikhil Jayakumar, Sunil P. Khatri, Rabi N. Mahapatra:
A low-jitter phase-locked resonant clock generation and distribution scheme. 487-490 - Zhenkun Yang, Kecheng Hao, Kai Cong, Sandip Ray, Fei Xie:
Equivalence checking for compiler transformations in behavioral synthesis. 491-494 - Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
On dynamic polymorphing of a superscalar core for improving energy efficiency. 495-498 - Li Lei, Kai Cong, Fei Xie:
Optimizing post-silicon conformance checking. 499-502 - Mihir Awatramani, Joseph Zambreno, Diane T. Rover:
Increasing GPU throughput using kernel interleaved thread block scheduling. 503-506 - Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
Stochastic functions using sequential logic. 507-510 - Nikolaos Strikos, Vasileios Kontorinis, Xiangyu Dong, Houman Homayoun, Dean M. Tullsen
Low-current probabilistic writes for power-efficient STT-RAM caches. 511-514 - Anshuman Gupta, Jack Sampson, Michael Bedford Taylor:
DR-SNUCA: An energy-scalable dynamically partitioned cache. 515-518 - Myoungjun Lee, Soontae Kim:
Performance-controllable shared cache architecture for multi-core soft real-time systems. 519-522
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