default search action
VLSI-SOC 2001: Montpellier, France
- Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes:
SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France. IFIP Conference Proceedings 218, Kluwer 2002, ISBN 1-4020-7148-5
Architecture for Signal & Image Processing
- P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou:
Two ASIC for Low and Middle Levels of Real Time Image Processing. VLSI-SOC 2001: 3-14 - Takashi Komuro, Masatoshi Ishikawa:
64×64 Pixels General Purpose Digital Vision Chip. VLSI-SOC 2001: 15-26 - Eric Senn, Eric Martin:
A Vision System on Chip for Industrial Control. VLSI-SOC 2001: 27-38 - Didier Demigny, Lounis Kessal, J. Pons:
Fast Recursive Implementation of the Gaussian Filter. VLSI-SOC 2001: 39-49
Dynamically Re-configurable Architectures
- Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC 2001: 51-62 - Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy:
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. VLSI-SOC 2001: 63-74 - Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou:
Reconfigurable Architecture Using High Speed FPGA. VLSI-SOC 2001: 75-86
CAD Tools
- Raul Camposano, Don MacMillen:
Design Technology for Systems-on-Chip. VLSI-SOC 2001: 87-96 - Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework. VLSI-SOC 2001: 97-108 - Morgan Hirosuke Miki, Motoki Kimura, Takao Onoye, Isao Shirakawa:
High Performance Java Hardware Engine and Software Kernel for Embedded Systems. VLSI-SOC 2001: 109-120 - João Cláudio Soares Otero, Flávio Rech Wagner:
An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures. VLSI-SOC 2001: 121-132 - David Bernard, Christian Landrault, Pascal Nouet:
Interconnect Capacitance Modelling in a VDSM CMOS Technology. VLSI-SOC 2001: 133-144
IP Design & Reuse
- Cristiano C. de Araújo, Edna Barros:
Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design. VLSI-SOC 2001: 145-156 - Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. VLSI-SOC 2001: 157-168 - Amaury Nève, Denis Flandre:
Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. VLSI-SOC 2001: 169-180
High Level Design Methodologies
- Braulio Adriano de Mello, Flávio Rech Wagner:
A Standardized Co-simulation Backbone. VLSI-SOC 2001: 181-192 - Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya:
Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. VLSI-SOC 2001: 193-204
Power Issues
- Catherine H. Gebotys, Radu Muresan:
Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model. VLSI-SOC 2001: 205-216 - Patricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin:
Power Consumption Model for the DSP OAK Processor. VLSI-SOC 2001: 217-228
Design for Specific Constraints
- Jean-Max Dutertre, F. M. Roche, Guy Cathébras:
Integration of Robustness in the Design of a Cell. VLSI-SOC 2001: 229-239 - Vincent Beroulle, Laurent Latorre, M. Dardalhon, Coumar Oudéa, Guy Perez, Francis Pressecq, Pascal Nouet:
Impact of Technology Spreading on MEMS design Robustness. VLSI-SOC 2001: 241-251
Architectures
- Nuno Roma, Leonel Sousa:
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation. VLSI-SOC 2001: 253-264 - Stephen M. Pisuk, Peter Hsin-Yu Wu:
Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder. VLSI-SOC 2001: 265-276
Low Power, Low Voltage
- Kiyoo Itoh, Hiroyuki Mizuno:
Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC 2001: 277-288 - Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi:
Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. VLSI-SOC 2001: 289-300 - Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
Timing Issues
- Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324 - Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne:
Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
Advance in Mixed Signal
- Jung Hyun Choi, Sergio Bampi:
CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors. VLSI-SOC 2001: 337-347 - Christophe Lallement, François Pêcheux, Yannick Hervé:
A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor. VLSI-SOC 2001: 349-360
Verification & Validation
- Peer Johannsen, Rolf Drechsler:
Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374 - Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre:
Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387
Test
- Erik Jan Marinissen:
An Industrial Approach to Core-Based System Chip Testing. VLSI-SOC 2001: 389-400 - Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412 - René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424 - Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436 - Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski:
Built-in Test of Analog Non-Linear Circuits in a SOC Environment. VLSI-SOC 2001: 437-448
Sensors
- Bruno Casadei, Jean-Piere Le Normand, Yann Hu, Bernard Cunin:
Design of a Fast CMOS APS Imager for High Speed Laser Detections. VLSI-SOC 2001: 449-460 - Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing. VLSI-SOC 2001: 461-472
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: