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30th VLSI-SOC 2022: Patras, Greece
- 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022. IEEE 2022, ISBN 978-1-6654-9005-4
- Vasileios Leon, George Lentaris, Dimitrios Soudris, Simon Vellas, Mathieu Bernou:
Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications. 1-4 - Rupesh Raj Karn, Ibrahim Abe M. Elfadel
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Confidential Inference in Decision Trees: FPGA Design and Implementation. 1-6 - Nikolaos Georgiou, Panayiotis Kolios:
Accurate real-time UAV flight-mode classification. 1-6 - Mohammad Humam Khan, Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi:
Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks. 1-6 - Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas
Efficient Dynamic Logic Magnitude Comparators. 1-5 - Mahdi Zahedi, Taha Shahroodi, Geert Custers, Abhairaj Singh, Stephan Wong, Said Hamdioui:
System Design for Computation-in-Memory: From Primitive to Complex Functions. 1-6 - Stian Gerlach Sørensen, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz:
Generation of Formal CPU Profiles for Embedded Systems. 1-6 - Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. 1-6 - Anastasios Michailidis
Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking. 1-6 - Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. 1-2 - Salvatore Levantino:
Frequency Synthesizers for 5G Applications. 1-4 - Nils Bosbach
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. 1-6 - Nikolaos Chatzivangelis
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. 1-6 - P. Esmaeili, Timothy Martin, Shawki Areibi, Gary Gréwal:
Guiding FPGA Detailed Placement via Reinforcement Learning. 1-6 - Dimitrios Samaras
A novel wide frequency range 65nm CMOS VCO. 1-4 - Gourav Datta, Souvik Kundu, Zihan Yin, Joe Mathai, Zeyu Liu, Zixu Wang, Mulin Tian, Shunlin Lu, Ravi Teja Lakkireddy, Andrew G. Schmidt, Wael Abd-Almageed, Ajey P. Jacob, Akhilesh R. Jaiswal, Peter A. Beerel
P2M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking. 1-6 - Yogesh Kumar, S. Sivakumar, John Jose:
ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches. 1-6 - Vinicius Zanandrea
Exploring Approximate Computing Approaches to Design Power-efficient Multipliers. 1-2 - Elissaios-Alexios Papatheofanous, Ph. Tziolos, V. Kalekis, Tzouma Amrou, George E. Konstantoulakis, Georgios Venitourakis, Dionysios I. Reisis:
SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images. 1-4 - Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. 1-6 - Jose Cayo, Ioannis Vourkas, Antonio Rubio:
A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM. 1-4 - Kritanta Saha, Pritha Banerjee
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. 1-6 - Akshay Sarman, Alwin Shaju, Rose George Kunthara
RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. 1-6 - Imlijungla Longchar, Palash Das, Hemangee K. Kapoor:
ZaLoBI: Zero avoiding Load Balanced Inference accelerator. 1-6 - Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs. 1-2 - J. Fernández-Aragón
Design and characterisation of a Physically Unclonable Function on FPGA using second-order compensated measurement. 1-2 - U. Esteban Eraso, Carlos Sánchez-Azqueta
A CMOS 4-bit Digitally Programmable Phase Shifter for the K-band. 1-2 - Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou:
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. 1-6 - Halil Kükner, Gökhan Kaplayan, Ahmet Efe, Mehmet Ali Gülden:
RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support. 1-6 - Johannes W. Farias, Diego V. Cirilo do Nascimento
Speculative guardband: exploiting critical-delay variations across cached instructions. 1-2 - Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas:
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency. 1-5 - Pedro Aquino Silva, Mateus Grellert
Exploring Approximate Comparator Circuits on Power Efficient Design of Decision Trees. 1-6 - Chun-Jen Tsai, Yi-De Lee:
Embedded TCP/IP Controller for a RISC-V SoC. 1-6 - Ashwin Bhat
Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge. 1-6 - Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat
Routability-Driven Detailed Placement Using Reinforcement Learning. 1-2 - Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesús Gutiérrez, Milos Krstic
High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS. 1-6 - Panagiotis Gkoutis, Georgios Konidas, Grigorios Kalivas:
30 GHz Front-End with Adaptively Biased PA and Current Steering LNA for Phased Array Systems. 1-6 - Jonathan Merk, Changhai Lin, Matthias Kamuf:
Assessing IMD of a Direct-to-RF Platform. 1-2 - Muhammad Awais, Marco Platzner:
Automated Framework for Fast Synthesis of Approximate Hardware Accelerators. 1-2 - Konstantinos Falis, Andreas Tsiougkos
Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT Systems. 1-6 - Konstantinos D. Katsanos
Secrecy Spectral Efficiency Optimization in RIS-Enabled MIMO Communication Systems. 1-6 - Shahzad Muzaffar, Ibrahim Abe M. Elfadel
Logic Locking of Finite-State Machines Using Transition Obfuscation. 1-6 - Nathan Laubeuf:
Analog Compute in Memory and Breaking Digital Number Representations. 1-2 - Carlos Fernandez, Ioannis Vourkas:
On the Design and Development of a ReRAM-based Computational Memory Prototype. 1-2 - Vasileios Manouras
A Wideband High-Gain Power Amplifier Operating in the D Band. 1-5 - Endri Kaja, Nicolas Gerlin, Monideep Bora
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. 1-6 - Antonis M. Paschalis, Panagiotis Chatziantoniou, Dimitris Theodoropoulos, Antonis Tsigkanos, Nektarios Kranitis:
High-Performance Hardware Accelerators for Next Generation On-Board Data Processing. 1-4 - Konstantina Koliogeorgi, Dimitris Mylonakis, Sotirios Xydis, Dimitrios Soudris
High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images. 1-6 - Anteneh Gebregiorgis, Abhairaj Singh, Sumit Diware, Rajendra Bishnoi, Said Hamdioui:
Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs. 1-6 - Foroozan Karimzadeh, Arijit Raychowdhury:
Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge Distillation. 1-6 - Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán:
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. 1-6 - Vasileios Leon, Elissaios-Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios I. Reisis, Dimitrios Soudris:
Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space. 1-6 - Nicolas Gerlin, Endri Kaja, Monideep Bora
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. 1-6 - Alexander Fusco
A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs. 1-6 - Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. 1-6 - Jorge Marqués-García
Modeling frequency response of gm-boosted inductorless Common-Gate LNA. 1-2 - Shubham Kumar
Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing. 1-6 - Carlos Fernandez, Ioannis Vourkas:
Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM. 1-6 - Elif Bilge Kavun:
A Power Reduction Technique Based on Linear Transformations for Block Ciphers. 1-6 - Chirag Sudarshan, Taha Soliman, Thomas Kämpfe
FeFET versus DRAM based PIM Architectures: A Comparative Study. 1-6 - Theo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit:
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge. 1-6 - Christopher Chuvalas, Ranga Vemuri:
FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. 1-6 - Georgios Flamis, Stavros Kalapothas, Paris Kitsos:
FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal. 1-5 - Rupali Hongekar, Ankita Gupta, Jayakrishna Guddeti, Meghashyam Ashwathnarayan:
Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System Modelling. 1-5 - Gaurav Kumar
Power Analysis Attack on Locking SIB based IJTAG Achitecture. 1-6 - Anu Asokan:
A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs. 1-6 - Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon:
An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. 1-6 - Pedro Aquino Silva, Mateus Grellert
Approximation Workflow for Energy-Efficient Comparators in Decision Tree Applications. 1-2 - Georgios Kottaras, Theodoros Sarris, Athanasios M. Psomoulis, Ilias Ioakeimidis, Angelos Papathanasiou, David Pitchford, Ingmar Sandberg
A low-power, radiation-hardened Single Event Effect rate detection System on a Chip for Real Time Monitoring of Single Event Effects on Low Earth Orbit satellites. 1-6 - Nahla A. El-Araby
Run Time Power and Accuracy Management with Approximate Circuits. 1-6 - Samuele Germiniani, Graziano Pravadelli:
Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions. 1-6 - George S. Vergos, Vasiliki Gogolou, C. Panagiotopoulou, A. Avgoustidis, Thomas Noulis, Kostas Siozios, Stilianos Siskos:
Machine Learning based Power Converter Large Signal Simulation for Energy Harvesting Applications. 1-5 - Simranjeet Singh
PA-PUF: A Novel Priority Arbiter PUF. 1-6 - Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. 1-6 - Cecil Accetti
Architectural Support for Functional Programming. 1-2 - C. del Río Bueno, U. Esteban Eraso, Carlos Sánchez-Azqueta
A 18-27 GHz Programmable Gain Amplifier in 65-nm CMOS technology. 1-2 - Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh:
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking. 1-6 - Milad Eslaminia, Sébastien Le Beux:
Toward Large Scale All-Optical Spiking Neural Networks. 1-6 - Nikolaos Kefalas, George Theodoridis:
An FPGA implementation of the VESA Display Stream Compression decoder. 1-6 - Can Aknesil, Elena Dubrova:
Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers. 1-6 - Rolf Drechsler
Preserving Design Hierarchy Information for Polynomial Formal Verification. 1-7 - Foroozan Karimzadeh, Arijit Raychowdhury:
Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity. 1-2 - Nikolaos Vasileiadis, Alexandros Mavropoulis, Panagiotis Loukas, Pascal Normand
Substrate Effect on Low-frequency Noise of synaptic RRAM devices. 1-5 - Artem Glukhov, Nicola Lepri, Valerio Milo, Andrea Baroni
End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays. 1-5 - Asmae El Arrassi, Anteneh Gebregiorgis, Anass El Haddadi, Said Hamdioui:
Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM). 1-6 - Renjie Chen, Aaron Stillmaker, Bevan M. Baas:
Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder. 1-6 - Evangelos Vlachos, Kostas Blekos:
Quantum Computing-Assisted Channel Estimation for Massive MIMO mmWave Systems. 1-6 - Alexander El-Kady, Apostolos P. Fournaris, Evangelos Haleplidis, Vassilis Paliouras
High-Level Synthesis design approach for Number-Theoretic Multiplier. 1-6 - Jonas Gava, Ricardo Reis, Luciano Ost:
Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices. 1-2 - Kyriaki Tsantikidou, Nicolas Sklavos
Flexible Security and Privacy, System Architecture for IoT, in Healthcare. 1-6
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