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Geert Hellings
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- affiliation: imec, Leuven, Belgium
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2020 – today
- 2024
- [c37]Nesara Eranna Bethur
, Pruek Vanna-Iampikul
GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC 2024: 287:1-287:6 - [c36]Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS 2024: 1-6 - [c35]S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). VLSI Technology and Circuits 2024: 1-2 - [c34]Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert:
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j6]Dawit Burusie Abdi
3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2858-2867 (2023) - [c33]Subrat Mishra, Sankatali Venkateswarlu
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS 2023: 1-7 - [c32]Michiel Vandemaele, Ben Kaczer, Erik Bury, Jacopo Franco, Adrian Chasin, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken
Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper. IRPS 2023: 1-10 - [c31]Wen-Chieh Chen
Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs. VLSI Technology and Circuits 2023: 1-2 - [c30]Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2 - [c29]S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert:
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j5]Giuliano Sisto
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1497-1506 (2022) - [c28]Gautam Gaddemane, Krishna K. Bhuwalka, Philippe Matagne, Gerhard Rzepa, Maarten L. Van De Put, Sybren Santermans, Oskar Baumgartner
Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology. ESSDERC 2022: 265-268 - [c27]Michiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Erik Bury, Adrian Vaisman Chasin, Jacopo Franco, Alexander Makarov, Hans Mertens, Geert Hellings, Guido Groeseneken
Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs. IRPS 2022: 6 - [c26]Stanislav Tyaginov, Aryan Afzalian, Alexander Makarov, Alexander Grill, Michiel Vandemaele, Maksim Cherenev, Mikhail I. Vexler, Geert Hellings, Ben Kaczer:
On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors. IRPS 2022: 11 - [c25]Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert:
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. VLSI Technology and Circuits 2022: 365-366 - [c24]Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert:
Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters. VLSI Technology and Circuits 2022: 371-372 - [c23]Rongmei Chen, Giuliano Sisto
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - [c22]Kateryna Serbulova
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits 2022: 431-432 - 2021
- [c21]Amita Rawat
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSCIRC 2021: 55-58 - [c20]Amita Rawat
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSDERC 2021: 55-58 - [c19]Gerhard Rzepa, Markus Karner, Oskar Baumgartner
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies. IRPS 2021: 1-6 - 2020
- [c18]Stanislav Tyaginov, Alexander Grill, Michiel Vandemaele, Tibor Grasser, Geert Hellings, Alexander Makarov, Markus Jech, Dimitri Linten, Ben Kaczer:
A Compact Physics Analytical Model for Hot-Carrier Degradation. IRPS 2020: 1-7
2010 – 2019
- 2019
- [c17]Alexander Makarov, Dimitri Linten, Stanislav Tyaginov, Ben Kaczer, Philippe Roussel, Adrian Vaisman Chasin, Michiel Vandemaele, Geert Hellings, Al-Moatasem El-Sayed
Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants. ESSDERC 2019: 262-265 - [c16]Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marko Simicic
CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. IRPS 2019: 1-7 - [c15]Geert Hellings
Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD Using TLP. IRPS 2019: 1-6 - [c14]Gaspard Hiblot, Yefan Liu, Geert Hellings, Geert Van der Plas:
Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage. IRPS 2019: 1-5 - [c13]Alexander Makarov, Ben Kaczer, Philippe Roussel, Adrian Vaisman Chasin, Alexander Grill, Michiel Vandemaele, Geert Hellings, Al-Moatasem El-Sayed, Tibor Grasser, Dimitri Linten, Stanislav Tyaginov:
Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs. IRPS 2019: 1-7 - 2018
- [j4]Shimpei Yamaguchi, Liesbeth Witters, Jérôme Mitard, Geert Eneman, Geert Hellings, Andriy Hikavyy, Roger Loo
Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. Microelectron. Reliab. 83: 157-161 (2018) - [j3]Gerhard Rzepa
Comphy - A compact-physics framework for unified modeling of BTI. Microelectron. Reliab. 85: 49-65 (2018) - [c12]Bertrand Parvais
Scaling CMOS beyond Si FinFET: an analog/RF perspective. ESSDERC 2018: 158-161 - [c11]Marko Simicic
ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology. ESSDERC 2018: 194-197 - 2017
- [c10]Mirko Scholz, Geert Hellings, Shih-Hung Chen, Dimitri Linten:
Tunable ESD clamp for high-voltage power I/O pins of a battery charge circuit in mobile applications. ESSDERC 2017: 248-251 - [c9]Nian Wang, Shih-Hung Chen, Geert Hellings, Kris Myny
ESD characterisation of a-IGZO TFTs on Si and foil substrates. ESSDERC 2017: 276-279 - 2016
- [j2]Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten:
Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC. Microelectron. Reliab. 57: 53-58 (2016) - 2015
- [c8]Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen
Processing active devices on Si interposer and impact on cost. 3DIC 2015: TS11.2.1-TS11.2.4 - [c7]Roman Boschke, Guido Groeseneken
ESD protection diodes in optical interposer technology. ICICDT 2015: 1-4 - [c6]Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten, Roman Boschke:
Impact of local interconnects on ESD design. ICICDT 2015: 1-4 - [c5]Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of fin shape variability on device performance towards 10nm node. ICICDT 2015: 1-4 - [c4]Zhigang Ji, Dimitri Linten, Roman Boschke, Geert Hellings, S. H. Chen, AliReza Alian, D. Zhou, Yves Mols, Tsvetan Ivanov, Jacopo Franco, Ben Kaczer, X. Zhang, R. Gao, Jianfu Zhang
ESD characterization of planar InGaAs devices. IRPS 2015: 3 - [c3]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2013
- [c2]Geert Hellings, Shih-Hung Chen, Dimitri Linten, Mirko Scholz, Guido Groeseneken
Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies. CICC 2013: 1-4 - 2012
- [c1]Jacopo Franco
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. ICICDT 2012: 1-4 - 2010
- [j1]Brahim Benbakhti, J. S. Ayubi-Moak, Karol Kalna
Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures. Microelectron. Reliab. 50(3): 360-364 (2010)
Coauthor Index
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