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Stefaan Van Huylenbroeck
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2010 – 2019
- 2019
- [c8]Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne
:
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC 2019: 1-6 - 2018
- [c7]Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne
TSV process-induced MOS reliability degradation. IRPS 2018: 5 - 2016
- [c6]Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. 3DIC 2016: 1-4 - 2015
- [c5]Joke De Messemaeker, O. Varela Pedreira
Impact of oxide liner properties on TSV Cu pumping and TSV stress. IRPS 2015: 4 - [c4]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2014
- [j1]Yunlong Li, Stefaan Van Huylenbroeck, Els Van Besien, Xiaoping Shi, Chen Wu, Michele Stucchi, Gerald Beyer, Eric Beyne
Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. Microelectron. Reliab. 54(9-10): 1949-1952 (2014) - [c3]Fumihiro Inoue
Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias. 3DIC 2014: 1-4 - 2012
- [c2]Christoph Kerner, Ivan Ciofi, Thomas Chiarella, Stefaan Van Huylenbroeck:
Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques. ESSDERC 2012: 221-225
2000 – 2009
- 2009
- [c1]Stefaan Decoutere, Stefaan Van Huylenbroeck, Bernd Heinemann, Alexander Fox, Pascal Chevalier
Pushing the speed limits of SiGe: C HBTs up to 0.5 Terahertz. CICC 2009: 347-354
Coauthor Index
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