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Nils Wistoff
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2020 – today
- 2024
- [j2]Luca Valente
, Alessandro Nadalini
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2266-2279 (2024) - [c7]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i11]Luca Valente, Alessandro Nadalini, Asif Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation. CoRR abs/2401.03531 (2024) - [i10]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR abs/2406.15068 (2024) - [i9]Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi:
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. CoRR abs/2407.19895 (2024) - [i8]Nils Wistoff, Gernot Heiser, Luca Benini:
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning. CoRR abs/2409.07576 (2024) - [i7]Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini:
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems. CoRR abs/2410.07798 (2024) - 2023
- [j1]Nils Wistoff
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. IEEE Trans. Computers 72(5): 1420-1430 (2023) - [c6]Luca Valente
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS 2023: 1-12 - [c5]Luca Cuomo, Claudio Scordino, Alessandro Ottaviano
Towards a RISC-V Open Platform for Next-generation Automotive ECUs. MECO 2023: 1-8 - [c4]Marcelo Orenes-Vera
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. MICRO 2023: 871-885 - [i6]Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino:
Towards a RISC-V Open Platform for Next-generation Automotive ECUs. CoRR abs/2307.04148 (2023) - [i5]Scott Buckley, Robert Sison
Proving the Absence of Microarchitectural Timing Channels. CoRR abs/2310.17046 (2023) - 2022
- [c3]Matteo Perotti, Matheus A. Cavalcante
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP 2022: 43-51 - [c2]Michael Rogenmoser
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. ISVLSI 2022: 398-401 - [i4]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini:
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. CoRR abs/2202.12029 (2022) - [i3]Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini:
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. CoRR abs/2205.12580 (2022) - [i2]Matteo Perotti, Matheus A. Cavalcante
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR abs/2210.08882 (2022) - 2021
- [c1]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser:
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. DATE 2021: 627-632 - 2020
- [i1]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser:
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. CoRR abs/2005.02193 (2020)
Coauthor Index
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