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Luca Colagrande
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2020 – today
- 2024
- [c3]Paul Scheffler
, Luca Colagrande
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. DAC 2024: 251:1-251:6 - [c2]Luca Colagrande
Optimizing Offload Performance in Heterogeneous MPSoCs. DATE 2024: 1-2 - [c1]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i4]Luca Colagrande, Luca Benini:
Optimizing Offload Performance in Heterogeneous MPSoCs. CoRR abs/2404.01908 (2024) - [i3]Paul Scheffler, Luca Colagrande, Luca Benini:
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. CoRR abs/2404.05303 (2024) - [i2]Viviane Potocnik, Luca Colagrande, Tim Fischer, Luca Bertaccini, Daniele Jahier Pagliari, Alessio Burrello, Luca Benini:
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform. CoRR abs/2405.19284 (2024) - [i1]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR abs/2406.15068 (2024)
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