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Paul Scheffler
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2020 – today
- 2024
- [j4]Thomas Benz
, Michael Rogenmoser
A High-Performance, Energy-Efficient Modular DMA Engine Architecture. IEEE Trans. Computers 73(1): 263-277 (2024) - [c8]Simone Manoni
NARS: Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores. CF (Companion) 2024 - [c7]Paul Scheffler
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. DAC 2024: 251:1-251:6 - [c6]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. DATE 2024: 1-6 - [c5]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i12]Paul Scheffler, Luca Colagrande, Luca Benini:
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. CoRR abs/2404.05303 (2024) - [i11]Philippe Sauter, Thomas Benz, Paul Scheffler, Zerun Jiang, Beat Muheim, Frank K. Gürkaynak, Luca Benini:
Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC. CoRR abs/2405.03523 (2024) - [i10]Philippe Sauter, Thomas Benz, Paul Scheffler, Frank K. Gürkaynak, Luca Benini:
Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? CoRR abs/2405.04257 (2024) - [i9]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR abs/2406.15068 (2024) - [i8]Paul Scheffler, Philippe Sauter, Thomas Benz, Frank K. Gürkaynak, Luca Benini:
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS. CoRR abs/2406.15107 (2024) - 2023
- [j3]Alessandro Ottaviano
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3777-3781 (2023) - [j2]Paul Scheffler
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. IEEE Trans. Parallel Distributed Syst. 34(12): 3147-3161 (2023) - [c4]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. DATE 2023: 1-6 - [i7]Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini:
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. CoRR abs/2305.04760 (2023) - [i6]Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-performance, Energy-efficient Modular DMA Engine Architecture. CoRR abs/2305.05240 (2023) - [i5]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. CoRR abs/2305.05559 (2023) - [i4]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. CoRR abs/2311.10378 (2023) - 2022
- [c3]Gianna Paulin
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI 2022: 44-49 - [i3]Gianna Paulin, Matheus A. Cavalcante
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR abs/2209.00889 (2022) - [i2]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. CoRR abs/2211.10409 (2022) - 2021
- [c2]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. DATE 2021: 1787-1792 - [c1]Samuel Riedel
Banshee: A Fast LLVM-Based RISC-V Binary Translator. ICCAD 2021: 1-9 - 2020
- [j1]Ines Schulze-Horn, Sabrina Hueren, Paul Scheffler, Holger Schiele:
Artificial Intelligence in Purchasing: Facilitating Mechanism Design-based Negotiations. Appl. Artif. Intell. 34(8): 618-642 (2020) - [i1]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. CoRR abs/2011.08070 (2020)
Coauthor Index
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