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Shiro Dosho
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2020 – today
- 2024
- [j24]Aravind Tharayil Narayanan, Ludovico Minati, Aran Hagihara, Jun Kobayashi, Toshihiro Shimura, Yoichi Kawano, Parthojit Chakraborty, Jim Bartels, Korkut Kaan Tokgoz, Shiro Dosho, Toshihide Suzuki, Hiroyuki Ito:
A neural network-based DPD coefficient determination for PA linearization in 5G and beyond-5G mmWave systems. IEICE Electron. Express 21(10): 20240186 (2024) - 2023
- [c14]Parthojit Chakraborty, Kazuki Maari, Jim Bartels, Alexandre Varieras, Aravind Tharayil Narayanan, Ludovico Minati, Shiro Dosho, Hiroyuki Ito:
Towards Digital Synthesis of Variable Q-Factor Direct-Conversion for Low-Power Edge Sensing. SENSORS 2023: 1-4 - [c13]Shiro Dosho, Ludovico Minati, Kazuki Maari, Hiroyuki Ito:
A Compact 0.9uW Direct-Conversion Frequency Analyzer for Speech Recognition with Wide-Range Q-Controlable Bandpass Rectifier. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2019
- [j23]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
, Chip-Hong Chang
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - 2018
- [j22]Motohiro Takayasu, Shiro Dosho, Hiroyuki Ito, Daisuke Yamane
A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers. IEICE Electron. Express 15(2): 20171227 (2018) - 2017
- [j21]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. 100-C(6): 560-567 (2017) - [j20]Sho Ikeda
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. IEEE J. Solid State Circuits 52(4): 1123-1133 (2017) - [c12]Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu:
Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. ASP-DAC 2017: 43-44 - 2016
- [c11]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC 2016: 141-144 - [c10]Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu:
An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. VLSI Circuits 2016: 1-2 - 2015
- [j19]Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid State Circuits 50(6): 1372-1381 (2015) - [j18]Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50(11): 2741-2749 (2015) - 2014
- [c9]Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC 2014: 216-217 - 2013
- [j17]Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells. IEICE Trans. Electron. 96-C(6): 813-819 (2013) - [c8]Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC 2013: 272-273 - 2012
- [j16]Shiro Dosho:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 429 (2012) - [j15]Koji Obata, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho:
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 471-478 (2012) - [j14]Shiro Dosho:
Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters. IEICE Trans. Electron. 95-C(4): 421-431 (2012) - [j13]Shiro Dosho:
Continuous-Time Delta-Sigma Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey. IEICE Trans. Electron. 95-C(6): 978-998 (2012) - [j12]Shinichiro Uemura, Yukio Hiraoka, Takayuki Kai, Shiro Dosho:
Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. IEEE J. Solid State Circuits 47(4): 810-816 (2012) - [j11]Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho:
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. IEEE J. Solid State Circuits 47(11): 2773-2782 (2012) - [c7]Kazuo Matsukawa, Koji Obata, Yosuke Mitani, Shiro Dosho:
A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method. VLSIC 2012: 160-161 - 2011
- [j10]Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa:
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. IEEE J. Solid State Circuits 46(4): 986-991 (2011) - [c6]Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa:
A time-domain architecture and design method of high speed A-to-D converters with standard cells. A-SSCC 2011: 353-356 - 2010
- [j9]Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa:
A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. IEEE J. Solid State Circuits 45(4): 697-706 (2010) - [j8]Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho:
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback. IEEE J. Solid State Circuits 45(6): 1150-1158 (2010) - [c5]Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho:
A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver. CICC 2010: 1-4
2000 – 2009
- 2009
- [j7]Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa:
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. IEEE J. Solid State Circuits 44(3): 763-774 (2009) - [c4]Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho:
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC 2009: 690-695 - [c3]Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho:
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage. ISSCC 2009: 404-405 - 2008
- [j6]Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho:
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. IEEE J. Solid State Circuits 43(4): 831-843 (2008) - 2007
- [j5]Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie:
An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. IEICE Trans. Electron. 90-C(6): 1197-1202 (2007) - 2006
- [j4]Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa:
A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. IEICE Trans. Electron. 89-C(6): 739-745 (2006) - [c2]Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori:
A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface. ISSCC 2006: 1286-1295 - [c1]Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie:
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution. ISSCC 2006: 2422-2431 - 2005
- [j3]Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa:
A background optimization method for PLL by measuring phase jitter performance. IEEE J. Solid State Circuits 40(4): 941-950 (2005) - 2002
- [j2]Shiro Dosho, Naoshi Yanagisawa, Seiji Watanabe, Takahiro Bokui, Kazuhiko Nishikawa:
Development of a CMOS Data Recovery PLL for DVD-ROMx14. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 764-769 (2002) - [j1]Shiro Dosho, Takashi Morie, Hirokuni Fujiyama:
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. IEEE J. Solid State Circuits 37(5): 559-565 (2002)
Coauthor Index
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