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Daniel Arumí
Person information
- affiliation: Universitat Politècnica De Catalunya, Barcelona, Spain
- affiliation (former): Universitat Politècnica De Catalunya, Barcelona, Spain
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2020 – today
- 2024
- [c16]V. Mahboubi
, Á. Gómez, Antonio Calomarde, Daniel Arumí, R. Rodríguez, Salvador Manich:
Engineering UGR-VCMTCF RRAM Model for Adjusting to TiN/Ti/HfO2/W Devices. DCIS 2024: 1-6 - [c15]V. Mahboubi, Á. Gómez, Antonio Calomarde, Daniel Arumí, R. Rodríguez, Salvador Manich:
On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET. IOLTS 2024: 1-7 - 2023
- [j10]Maryam Akbari
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs. IEEE Access 11: 66682-66693 (2023) - 2022
- [c14]V. Mahboubi
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data. DCIS 2022: 1-6 - 2021
- [c13]P. Albiol, Salvador Manich, Daniel Arumí, Rosa Rodríguez-Montañés, Álvaro Gómez-Pau:
Low Cost AES Protection Against DPA Using Rolling Codes. DCIS 2021: 1-6 - [c12]Binbin Yang
Simulation of serial RRAM cell based on a Verilog-A compact model. DCIS 2021: 1-6 - 2020
- [j9]Binbin Yang, Nuo Xu
A forming-free ReRAM cell with low operating voltage. IEICE Electron. Express 17(22): 20200343 (2020)
2010 – 2019
- 2019
- [j8]Rosa Rodríguez-Montañés
Postbond Test of Through-Silicon Vias With Resistive Open Defects. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2596-2607 (2019) - 2016
- [j7]Daniel Arumí
Prebond Testing of Weak Defects in TSVs. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1503-1514 (2016) - [j6]Daniel Arumí
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1739-1748 (2016) - [c11]Daniel Arumí
RRAM based cell for hardware security applications. IVSW 2016: 1-6 - 2014
- [c10]Rosa Rodríguez-Montañés, Daniel Arumí
Post-bond test of Through-Silicon Vias with open defects. ETS 2014: 1-6 - [c9]Daniel Arumí
Pre-bond testing of weak defects in TSVs. IOLTS 2014: 31-36 - 2013
- [j5]Daniel Arumí
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 301-312 (2013) - [c8]Daniel Arumí
BIST architecture to detect defects in tsvs during pre-bond testing. ETS 2013: 1 - 2011
- [j4]Daniel Arumí
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1911-1922 (2011) - [j3]Daniel Arumí
Gate Leakage Impact on Full Open Defects in Interconnect Lines. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2209-2220 (2011) - 2010
- [c7]Rosa Rodríguez-Montañés, Daniel Arumí
Diagnosis of full open defects in interconnect lines with fan-out. ETS 2010: 233-238
2000 – 2009
- 2009
- [j2]Daniel Arumí
Delay caused by resistive opens in interconnecting lines. Integr. 42(3): 286-293 (2009) - 2008
- [j1]Daniel Arumí
Experimental Characterization of CMOS Interconnect Open Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 123-136 (2008) - [c6]Rosa Rodríguez-Montañés, Daniel Arumí
Time-dependent Behaviour of Full Open Defects in Interconnect Lines. ITC 2008: 1-10 - [c5]Daniel Arumí
Full Open Defects in Nanometric CMOS. VTS 2008: 119-124 - 2007
- [c4]Daniel Arumí
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS 2007: 145-150 - [c3]Rosa Rodríguez-Montañés, Daniel Arumí
Diagnosis of Full Open Defects in Interconnecting Lines. VTS 2007: 158-166 - 2005
- [c2]Daniel Arumí
Defective behaviours of resistive opens in interconnect lines. ETS 2005: 28-33 - 2003
- [c1]Daniel Arumí-Delgado
Process-variability aware delay fault testing of ΔVT and weak-open defects. ETW 2003: 85-90
Coauthor Index
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