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Haruo Kobayashi 0001
Person information
- affiliation: Gunma University, Japan
Other persons with the same name
- Haruo Kobayashi 0002 — Kawasaki University of Medical Welfare, Okayama, Japan (and 1 more)
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2020 – today
- 2024
- [j54]Haruo Kobayashi:
How the Author's Group Came Up with Ideas in Analog/Mixed-Signal Circuit and System Area. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 681-699 (2024) - [c133]Haruo Kobayashi, Naoki Tsukahara, Keno Sato, Takashi Oshima
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Innovative Practices Session at VLSI Test Symposium 2024: Analog Testing Technologies for Digital Exploding Society. VTS 2024: 1 - 2023
- [j53]Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. IEICE Electron. Express 20(1): 20220470 (2023) - [j52]Lengkhang Nengvang, Shogo Katayama, Anna Kuwana, Kazufumi Naganuma, Kiyoshi Sasai, Akihisa Iikura, Akira Asao, Takuya Watanabe, Katsuaki Morishita, Haruo Kobayashi:
Relaxation DAC with positive and negative polarity output using high-pass filter. IEICE Electron. Express 20(4): 20220536 (2023) - [c132]Haruo Kobayashi:
Signal Generation Technologies for Analog/Mixed-Signal IC Testing. ASICON 2023: 1-4 - [c131]Haruo Kobayashi, Manato Hirai, Kakeru Otomo, Shogo Katayama, Xueyan Bai, Masashi Chiba, Zifei Xu, Dan Yao, Lengkhang Nengvang, Minh Tri Tran, Kanji Yoshihiro, Anna Kuwana, Takato Ooide, Hiroshi Tanimoto, Yuji Gendai, Jianglin Wei:
Back to the Analog Neural Network and Linear Circuit Theory. ASICON 2023: 1-4 - [c130]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. ITC 2023: 47-55 - [c129]Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. ITC-Asia 2023: 1-6 - 2022
- [j51]Yujie Zhao
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. J. Electron. Test. 38(1): 21-38 (2022) - [j50]Xueyan Bai, Shogo Katayama, Dan Yao, Anna Kuwana, Zifei Xu, Haruo Kobayashi:
Asynchronous capacitive SAR ADC based on Hopfield network. IEICE Electron. Express 19(18): 20220276 (2022) - [j49]Dan Yao, Xuanyan Bai, Shogo Katayama, Anna Kuwana, Kazuyuki Kawauchi, Haruo Kobayashi, Kouji Hirai, Akira Suzuki, Satoshi Yamada, Tomoyuki Kato, Ritsuko Kitakoga, Takeshi Shimamura, Gopal Adhikari, Nobuto Ono, Kazuhiro Miura, Shigeya Yamaguchi:
Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout. IEICE Electron. Express 19(24): 20220430 (2022) - [j48]Jianglin Wei, Anna Kuwana, Haruo Kobayashi, Kazuyoshi Kubo:
IEEE754 Binary32 Floating-Point Logarithmic Algorithms Based on Taylor-Series Expansion with Mantissa Region Conversion and Division. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(7): 1020-1027 (2022) - [c128]Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. ATS 2022: 37-42 - [c127]Gui-Yi Dong
Notch Frequency Generation Methods in Noise Spread Spectrum for Pulse Coding Switching DC-DC Converter. LASCAS 2022: 1-4 - [c126]Hao Yang Du, Jun-Ichi Matsuda, Anna Kuwana, Haruo Kobayashi:
Low Switching Loss Dual RESURF 40 V N-LDMOS with Grounded Field Plate for DC-DC Converters. MWSCAS 2022: 1-4 - [c125]Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa:
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS 2022: 1 - 2021
- [j47]Jianglin Wei
Floating-Point Inverse Square Root Algorithm Based on Taylor-Series Expansion. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2640-2644 (2021) - [c124]Minh Tri Tran, Anna Kuwana, Haruo Kobayashi:
Study of Behaviors of Motion Models in High-Order Systems. AIIoT 2021: 332-341 - [c123]Haruo Kobayashi, Xueyan Bai, Yujie Zhao, Shuhei Yamamoto, Dan Yao, Manato Hirai, Jianglin Wei, Shogo Katayama, Anna Kuwana:
Classical Mathematics and Analog/Mixed-Signal IC Design. ASICON 2021: 1-4 - [c122]Gui-Yi Dong
Adaptive Convergence Method of Notch Frequency in Noise Spread Spectrum for Pulse Coding Switching DC-DC Converter. ASICON 2021: 1-4 - [c121]Anna Kuwana, Jun-Ichi Matsuda, Haruo Kobayashi:
Analysis of Switching Characteristics of Wide SOA and High Reliability 100 V N-LDMOS Transistor with Dual RESURF and Grounded Field Plate Structure. ASICON 2021: 1-4 - [c120]Yuki Sekine, Shogo Katayama, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Multi-Output SEIPC Multiplied Boost Converter with Exclusive Control. ASICON 2021: 1-4 - [c119]Jianglin Wei, Anna Kuwana, Haruo Kobayashi, Kazuyoshi Kubo:
Divide and Conquer: Floating-Point Exponential Calculation Based on Taylor-Series Expansion. ASICON 2021: 1-4 - [c118]Shogo Katayama, Yudai Abe, Anna Kuwana, Koji Asami, Masahiro Ishida, Ryuya Ohta, Haruo Kobayashi:
Application of Residue Sampling to RF/AMS Device Testing. ATS 2021: 19-24 - [c117]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
High Precision Measurement of Sub-Nano Ampere Current in ATE Environment. ATS 2021: 139-140 - [c116]Minh Tri Tran
Study of Helix Functions and Multi-Source Rauch Filters. CCWC 2021: 1409-1416 - [c115]Minh Tri Tran
Study of Rauch Low-Pass Filters using Pascal's Triangle. ICEIC 2021: 1-4 - [c114]Gaku Ogihara, Takayuki Nakatani, Daisuke Iimori, Shogo Katayama, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Jianglin Wei, Kazumi Hatayama, Haruo Kobayashi:
Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production. ICECS 2021: 1-6 - [c113]Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi:
Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. IOLTS 2021: 1-6 - [c112]Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. ITC 2021: 284-288 - [c111]Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi:
Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. ITC 2021: 364-373 - [c110]Jianglin Wei, Anna Kuwana, Haruo Kobayashi, Kazuyoshi Kubo, Yuuki Tanaka:
Floating-Point Square Root Calculation Algorithm Based on Taylor-Series Expansion and Region Division. MWSCAS 2021: 774-778 - [c109]Minh Tri Tran, Anna Kuwana, Haruo Kobayashi:
Investigation of Behaviours of Kerwin-Huelsman-Newcomb Filters Using Nichols Charts of Self-Loop Function. MWSCAS 2021: 1007-1012 - 2020
- [j46]Md. Asadur Rahman
Activation Modeling and Classification of Voluntary and Imagery Movements From the Prefrontal fNIRS Signals. IEEE Access 8: 218215-218233 (2020) - [j45]Yifei Sun, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Pulse Coding Controlled Switching Converter that Generates Notch Frequency to Suit Noise Spectrum. IEICE Trans. Commun. 103-B(11): 1331-1340 (2020) - [c108]Jianglin Wei
Revisit to Floating-Point Division Algorithm Based on Taylor-Series Expansion. APCCAS 2020: 240-243 - [c107]Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei
Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers. ATS 2020: 1-6 - [c106]Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Accurate Testing of Precision Voltage Reference by DC-AC Conversion. ATS 2020: 1-2 - [c105]Yukiko Shibasaki, Koji Asami, Riho Aoki, Akemi Hatta, Anna Kuwana, Haruo Kobayashi:
Analysis and Design of Multi-Tone Signal Generation Algorithms for Reducing Crest Factor. ATS 2020: 1-6 - [c104]Yuanyang Du, Xueyan Bai, Manato Hirai, Shuhei Yamamoto, Anna Kuwana, Haruo Kobayashi, Kazuyoshi Kubo:
Digital-to-Analog Converter Architectures Based on Polygonal and Prime Numbers. ISOCC 2020: 7-8 - [c103]Manato Hirai, Hiroshi Tanimoto, Yuji Gendai, Shuhei Yamamoto, Anna Kuwana, Haruo Kobayashi:
Nonlinearity Analysis of Resistive Ladder-Based Current-Steering Digital-to-Analog Converter. ISOCC 2020: 9-10 - [c102]Yukiko Shibasaki, Koji Asami, Akemi Hatta, Riho Aoki, Anna Kuwana, Haruo Kobayashi:
Study on Crest Factor Controlled Multi-Tone Signal for Analog RF Circuit Testing. ISOCC 2020: 133-134 - [c101]Yudai Abe, Akio Iwabuchi, Jun-Ichi Matsuda, Anna Kuwana, Takashi Ida, Yukiko Shibasaki, Haruo Kobayashi:
Low Power Loss IGBT Driver Circuit Using Current Drive. ISOCC 2020: 135-136 - [c100]Souma Yamamoto, Kuswan Isam Ebisawa, Yudai Abe, Takashi Ida, Yukiko Shibasaki, Nobukazu Tsukiji, Anna Kuwana, Haruo Kobayashi, Akira Suzuki, Yukichi Todoroki, Toshihiko Kakinoki, Nobuto Ono, Kazuhiro Miura:
Operation and Stability Analysis of Temperature-Insensitive MOS Reference Current Source with Self-Bias Circuit. ISOCC 2020: 137-138 - [c99]Takashi Hosono, Lei Sha, Souma Yamamoto, Mayu Hirano, Takashi Ida, Anna Kuwana, Haruo Kobayashi, Yoichi Moroshima, Hiromichi Harakawa, Takeshi Oikawa:
Improved Nagata Current Source Insensitive to Temperature and Power Supply Voltage. ISOCC 2020: 151-152 - [c98]Lei Sha, Anna Kuwana, Masashi Horiguchi, Haruo Kobayashi:
Simple Reference Voltage Generation Circuit Insensitive to Temperature. ISOCC 2020: 242-243 - [c97]Minh Tri Tran
Ringing Test for Third-Order Ladder Low-Pass Filters. UEMCON 2020: 440-446 - [c96]Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake
Innovative Test Practices in Asia. VTS 2020: 1
2010 – 2019
- 2019
- [j44]Kiichi Niitsu
Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. IEICE Electron. Express 16(13): 20190218 (2019) - [c95]Yudai Abe, Shogo Katayama, Congbing Li, Anna Kuwana, Haruo Kobayashi:
Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number System. ASICON 2019: 1-4 - [c94]Riho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Evaluation of Null Method for Operational Amplifier Short-Time Testing. ASICON 2019: 1-4 - [c93]Koji Asami, Nene Kushita, Akemi Hatta, Minh Tri Tran
Analysis and Evaluation Method of RC Polyphase Filter. ASICON 2019: 1-4 - [c92]Manato Hirai, Shuhei Yamamoto, Hirotaka Arai, Anna Kuwana, Hiroshi Tanimoto, Yuji Gendai, Haruo Kobayashi:
Systematic Construction of Resistor Ladder Network for N-ary DACs. ASICON 2019: 1-4 - [c91]Shogo Katayama, Jing Li, Yifei Sun, Minh Tri Tran
Automatic Correction of Current Imbalance for Multi-Phase COT Ripple-Based Control DC-DC Converter. ASICON 2019: 1-4 - [c90]Shogo Katayama, Noriyuki Oiwa, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Output Voltage Ripple Reduction with Nosie Spread Spectrum for Dual-Phase LLC Resonant Converter. ASICON 2019: 1-4 - [c89]Haruo Kobayashi, Nene Kushita, Minh Tri Tran
Analog / Mixed-Signal / RF Circuits for Complex Signal Processing. ASICON 2019: 1-4 - [c88]Haruo Kobayashi, Kosuke Machida, Yuto Sasaki, Yusuke Osawa, Pengfei Zhang, Lei Sha, Yuki Ozawa, Anna Kuwana:
Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types. ASICON 2019: 1-4 - [c87]Anna Kuwana, Jun-Ichi Matsuda, Haruo Kobayashi:
Optimization of High Reliability and Wide SOA 100 V LDMOS Transistor with Low Specific On-Resistance. ASICON 2019: 1-4 - [c86]Yifei Sun, Minh Tri Tran
Pulse Coding Control Switching Converter with Adjustable Conversion Voltage Ratio Notch Frequency Generation in Noise Spectrum. ASICON 2019: 1-4 - [c85]Yifei Sun, Minh Tri Tran
EMI Noise Reduction and Output Ripple Cancellation for Full-Wave Type Soft-Switching Converter. ASICON 2019: 1-4 - [c84]Minh Tri Tran
Flat Pass-Band Method with Two RC Band-Stop Filters for 4-Stage Passive RC Polyphase Filter in Low-IF Receiver Systems. ASICON 2019: 1-4 - [c83]Minh Tri Tran
Overshoot Cancelation Based on Balanced Charge-Discharge Time Condition for Buck Converter in Mobile Applications. ASICON 2019: 1-4 - [c82]Minh Tri Tran
Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter. ASICON 2019: 1-4 - [c81]Shiyu Wang, Md. Zakir Hossain, Takaaki Suzuki, Kazuo Shinozuka, Natsuhiko Shimizu, Shunya Kitada, Ryo Ichige, Anna Kuwana, Haruo Kobayashi:
Graphene Biosensor for Saliva Protein Adsorption. ASICON 2019: 1-4 - [c80]Jiang-Lin Wei
High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm. ASICON 2019: 1-4 - [c79]Chen-Hao Zhang, Yifei Sun, Minh Tri Tran
Multi-Phase Full/Half Wave Type Resonant Converters with Automatic Current Balance against Element Variation. ASICON 2019: 1-4 - [c78]Yuto Sasaki, Kosuke Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion. ITC-Asia 2019: 1-6 - [c77]Yukiko Shibasaki, Koji Asami, Anna Kuwana, Kosuke Machida, Yuanyang Du, Akemi Hatta, Kazuyoshi Kubo, Haruo Kobayashi:
Crest Factor Controlled Multi-Tone Signals for Analog/Mixed-Signal IC Testing. ITC-Asia 2019: 7-12 - [c76]Yusuke Asada, Takahiko Shimizu, Yuji Gendai, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei
Innovative Test Practices in Japan. VTS 2019: 1 - 2018
- [j43]Peter Sarson, Tomonori Yanagida, Shohei Shibuya, Kosuke Machida, Haruo Kobayashi:
A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment. J. Electron. Test. 34(3): 215-232 (2018) - [j42]Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi:
A Study on Loop Gain Measurement Method Using Output Impedance in DC-DC Buck Converter. IEICE Trans. Commun. 101-B(9): 1940-1948 (2018) - [c75]Yuto Sasaki, Yujie Zhao, Anna Kuwana, Haruo Kobayashi:
Highly Efficient Waveform Acquisition Condition in Equivalent-Time Sampling System. ATS 2018: 197-202 - [c74]Kosuke Machida, Uni Ozawa, Yudai Abe, Haruo Kobayashi:
Time-to-Digital Converter Architectures Using Two Oscillators with Different Frequencies. ATS 2018: 203-208 - [c73]Tomonori Yanagida, Shohei Shibuya, Kosuke Machida, Koji Asami, Haruo Kobayashi:
Low-Distortion One-Tone and Two-Tone Signal Generation Using AWG Over Full Nyquist Region. ITC-Asia 2018: 91-96 - [c72]Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama:
Innovative practices on test in Japan. VTS 2018: 1 - 2017
- [j41]Peter Sarson
Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs. J. Electron. Test. 33(3): 295-303 (2017) - [c71]Haruo Kobayashi, Isao Shimizu, Nobukazu Tsukiji, Miho Arai, Kazuyoshi Kubo, Hitoshi Aoki:
Fundamental design tradeoff and performance limitation of electronic circuits based on uncertainty relationships. ASICON 2017: 549-552 - [c70]Yuki Ozawa, Takashi Ida, Richen Jiang, Shotaro Sakurai, Seiya Takigami, Nobukazu Tsukiji, Ryoji Shiota, Haruo Kobayashi:
SAR TDC Architecture with Self-Calibration Employing Trigger Circuit. ATS 2017: 94-99 - [c69]Jianlong Wang, Gopal Adhikari, Nobukazu Tsukiji, Mayu Hirano, Haruo Kobayashi, Keita Kurihara, Akihito Nagahama, Ippei Noda, Kohji Yoshii:
Equivalence between Nyquist and Routh-Hurwitz stability criteria for operational amplifier design. ISPACS 2017: 108-113 - [c68]Takashi Ida, Yuki Ozawa, Jiang Richen, Shotaro Sakurai, Seiya Takigami, Nobukazu Tsukiji, Hirotaka Arai, Ryoji Shiota, Haruo Kobayashi:
Architecture of high performance successive approximation time digitizer. ISPACS 2017: 456-461 - [c67]Yuki Ozawa, Takashi Ida, Shotaro Sakurai, Richen Jiang, Rino Takahashi, Haruo Kobayashi, Ryoji Shiota:
SAR TDC architecture for one-shot timing measurement with full digital implementation. ISPACS 2017: 462-467 - [c66]Yuki Ozawa, Takuya Arafune, Nobukazu Tsukiji, Haruo Kobayashi, Ryoji Shiota:
Study of jitter generators for high-speed I/O interface jitter tolerance testing. ISPACS 2017: 468-473 - [c65]Dan Yao, Yifei Sun, Masashi Higashino, Shaiful Nizam Bin Mohyar, Tomonori Yanagida, Takuya Arafune, Nobukazu Tsukiji, Haruo Kobayashi:
DAC linearity improvement with layout technique using magic and latin squares. ISPACS 2017: 616-621 - [c64]Hirotaka Arai, Takuya Arafune, Shohei Shibuya, Yutaro Kobayashi, Koji Asami, Haruo Kobayashi:
Fibonacci sequence weighted SAR ADC as golden section search. ISPACS 2017: 657-662 - [c63]Shotaro Sakurai, Seiya Takigami, Takashi Ida, Yuki Ozawa, Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi, Ryoji Shiota:
Study of multistage digital oscilloscope trigger circuit. ISPACS 2017: 663-668 - [c62]Richen Jiang, Gopal Adhikari, Yifei Sun, Dan Yao, Rino Takahashi, Yuki Ozawa, Nobukazu Tsukiji, Haruo Kobayashi, Ryoji Shiota:
Gray-code input DAC architecture for clean signal generation. ISPACS 2017: 669-674 - [c61]Yi Xiong, Yifei Sun, Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi:
Two-phase soft-switching DC-DC converter with voltage-mode resonant switch. ISPACS 2017: 735-740 - [c60]Yi Xiong, Koyo Asaishi, Natsuko Milli, Yifei Sun, Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi:
Constant on-time controlled four-phase buck converter via two ways of saw-tooth-wave circuit and PLL circuit. ISPACS 2017: 741-746 - [c59]Yasunori Kobori, Nobukazu Tsukiji, Takuya Arafune, Manimel Wadu Sahan, Dulara Yifei Sun, Nobukazu Takai, Haruo Kobayashi:
Noise spread spectrum with adjustable notch frequency in complex pulse coding controlled DC-DC converters. ISPACS 2017: 752-757 - [c58]Manimel Wadu Sahan Dulara, Nobukazu Tsukiji, Yasunori Kobori, Koyo Asaishi, Nobukazu Takai, Haruo Kobayashi:
Delay-time suppression technique for DC/DC buck converter using voltage mode PWM control. ISPACS 2017: 758-763 - [c57]Shotaro Sakurai, Nobukazu Tsukiji, Yasunori Kobori, Haruo Kobayashi:
Estimation of circuit component values in buck converter using efficiency curve. ISPACS 2017: 895-900 - [c56]Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi:
Low-distortion signal generation for analog/mixed-signal circuit testing with digital ATE. ITC-Asia 2017: 2-7 - [c55]Peter Sarson, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi:
A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithm. VTS 2017: 1-6 - 2016
- [c54]Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi:
Rectangular Waveform Generation with Harmonics Suppression. ATS 2016: 125 - [c53]Masahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar
I-Q signal generation techniques for communication IC testing and ATE systems. ITC 2016: 1-10 - 2015
- [j40]Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi:
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J. Electron. Test. 31(4): 419 (2015) - [j39]Shu Wu, Yasunori Kobori, Nobukazu Tsukiji, Haruo Kobayashi:
Transient Response Improvement of DC-DC Buck Converter by a Slope Adjustable Triangular Wave Generator. IEICE Trans. Commun. 98-B(2): 288-295 (2015) - [j38]Kiichi Niitsu
A CMOS PWM Transceiver Using Self-Referenced Edge Detection. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1145-1149 (2015) - [c52]Takuya Arafune, Yutaro Kobayashi, Shohei Shibuya, Haruo Kobayashi:
Fibonacci sequence weighted SAR ADC algorithm and its DAC topology. ASICON 2015: 1-4 - [c51]Miho Arai, Isao Shimizu, Haruo Kobayashi, Keita Kurihara, Shu Sasaki, Shohei Shibuya, Kiichi Niitsu
Finite aperture time effects in sampling circuit. ASICON 2015: 1-4 - [c50]Masashi Higashino, Hitoshi Aoki, Nobukazu Tsukiji, Masaki Kazumi, Takuya Totsuka, Haruo Kobayashi:
Study on maximum electric field modeling used for HCI induced degradation characteristic of LDMOS transistors. ASICON 2015: 1-4 - [c49]Yasunori Kobori, Takuya Arafune, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi:
Selectable notch frequencies of EMI spread spectrum using pulse modulation in switching converter. ASICON 2015: 1-4 - [c48]Yasunori Kobori, Taifeng Wang, Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi:
EMI reduction by analog noise spread spectrum in new ripple controlled converter. ASICON 2015: 1-4 - [c47]Masahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar, Takahiro Miki, Osamu Kobayashi:
Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniques. ASICON 2015: 1-4 - [c46]Yoshiki Niki, Shu Sasaki, Nobu Yamaguchi, Jian Kang, Takashi Kitahara, Haruo Kobayashi:
Flat passband gain design algorithm for 2nd-order RC polyphase filter. ASICON 2015: 1-4 - [c45]Shohei Shibuya, Yutaro Kobayashi, Haruo Kobayashi:
High-frequency low-distortion signal generation algorithm with arbitrary waveform generator. ASICON 2015: 1-4 - [c44]Yoshiki Sugawara, Nobukazu Takai, Masato Kato, Hiroaki Seki, Kento Suzuki, Haruo Kobayashi:
Automatic design of doubly-terminated RC polyphase filters by using distributed genetic algorithm. ASICON 2015: 1-4 - [c43]Yoshiki Sunaga, Naoya Shiraishi, Koyo Asaishi, Nobukazu Tsukiji, Yasunori Kobori, Nobukazu Takai, Haruo Kobayashi:
High efficiency single-inductor dual-output DC-DC converter with ZVS-PWM control. ASICON 2015: 1-4 - [c42]Kento Suzuki, Nobukazu Takai, Masato Kato, Hiroaki Seki, Yoshiki Sugawara, Haruo Kobayashi:
Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimization. ASICON 2015: 1-4 - [c41]Nobukazu Tsukiji, Hitoshi Aoki, Masaki Kazumi, Takuya Totsuka, Masashi Higashino, Haruo Kobayashi:
A study on HCI induced gate leakage current model used for reliability simulations in 90nm n-MOSFETs. ASICON 2015: 1-4 - [c40]Yutaro Kobayashi, Shohei Shibuya, Takuya Arafune, Shu Sasaki, Haruo Kobayashi:
SAR ADC design using Golden ratio weight algorithm. ISCIT 2015: 303-306 - 2014
- [j37]Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi:
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J. Electron. Test. 30(6): 653-663 (2014) - [j36]Haruo Kobayashi, Hitoshi Aoki, Kentaroh Katoh, Congbing Li:
Analog/mixed-signal circuit design in nano CMOS era. IEICE Electron. Express 11(3): 20142001 (2014) - [j35]Kiichi Niitsu
A low-offset cascaded time amplifier with reconfigurable inter-stage connection. IEICE Electron. Express 11(10): 20140203 (2014) - [c39]Fumitaka Abe, Yutaro Kobayashi, Kenji Sawada, Keisuke Kato, Osamu Kobayashi, Haruo Kobayashi:
Low-distortion signal generation for ADC testing. ITC 2014: 1-10 - 2013
- [j34]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. 29(6): 879-892 (2013) - [j33]Kiichi Niitsu
Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption. IEICE Electron. Express 10(11): 20130289 (2013) - [j32]Keisuke Kato, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, Kiichi Niitsu
Two-Tone Signal Generation for ADC Testing. IEICE Trans. Electron. 96-C(6): 850-858 (2013) - [j31]Kiichi Niitsu
A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines. IEICE Trans. Electron. 96-C(6): 920-922 (2013) - [c38]Kiichi Niitsu
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC 2013: 103-104 - [c37]Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh:
Digital Compensation for Timing Mismatches in Interleaved ADCs. Asian Test Symposium 2013: 134-139 - [c36]Kentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai:
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators. Asian Test Symposium 2013: 140-146 - 2012
- [j30]Kazuyuki Wakabayashi, Keisuke Kato, Takafumi Yamada, Osamu Kobayashi, Haruo Kobayashi, Fumitaka Abe, Kiichi Niitsu
Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator. J. Electron. Test. 28(5): 641-651 (2012) - [j29]Kiichi Niitsu
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. IEEE J. Solid State Circuits 47(11): 2701-2710 (2012) - [c35]Hong Gao, Lin Xing, Yasunori Kobori, Feng Zhao, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker, Kiichi Niitsu
DC-DC converter with continuous-time feed-forward Sigma-Delta modulator control. APCCAS 2012: 65-68 - [c34]Yasunori Kobori, Qiulin Zhu, Murong Li, Feng Zhao, Zachary Nosker, Shu Wu, Shaiful N. Mohyar, Masanori Onozawa, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
Single inductor dual output DC-DC converter design with exclusive control. APCCAS 2012: 436-439 - [c33]Guanglei Jin, Hao Chen, Chuan Gao, Yunpeng Zhang, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
Digitally-controlled Gm-C bandpass filter. APCCAS 2012: 531-534 - [c32]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu
Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS 2012: 671-674 - [c31]Kiichi Niitsu
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC 2012: 553-554 - [c30]Keisuke Kato, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, Kiichi Niitsu
Two-Tone Signal Generation for Communication Application ADC Testing. Asian Test Symposium 2012: 179-184 - [c29]Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium 2012: 185-190 - [c28]Kiichi Niitsu
Post-Silicon Jitter Measurements. Asian Test Symposium 2012: 258-263 - [c27]Kiichi Niitsu
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC 2012: 142-143 - 2011
- [j28]Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu
Design for Testability That Reduces Linearity Testing Time of SAR ADCs. IEICE Trans. Electron. 94-C(6): 1061-1064 (2011) - [j27]Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Satoshi Ito, Yohei Tan, Haruo Kobayashi:
Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. IEICE Trans. Electron. 94-C(7): 1233-1236 (2011) - [c26]Kiichi Niitsu
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. A-SSCC 2011: 201-204 - [c25]Masato Sakurai, Kiichi Niitsu
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. ISOCC 2011: 146-149 - 2010
- [j26]Hao San
Noise-Coupled Image Rejection Architecture of Complex Bandpass DeltaSigmaAD Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 390-394 (2010) - [j25]Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San
SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 415-423 (2010) - [c24]Satoshi Uemori, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
ADC linearity test signal generation algorithm. APCCAS 2010: 44-47 - [c23]Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San
Non-binary SAR ADC with digital error correction for low power applications. APCCAS 2010: 196-199 - [c22]Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Yohei Tan, Satoshi Ito, Haruo Kobayashi:
Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure. APCCAS 2010: 200-203 - [c21]Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu
SAR ADC that is configurable to optimize yield. APCCAS 2010: 374-377 - [c20]Kenji Takahashi, Hajime Yokoo, Shyunsuke Miwa, Kengo Tsushida, Hiroyuki Iwase, Kazuki Murakami, Nobukazu Takai, Haruo Kobayashi, Takahiro Odaguchi, Shigeki Takayama, Isao Fukai, Jun-Ichi Matsuda:
Single inductor DC-DC converter with bipolar outputs using charge pump. APCCAS 2010: 460-463 - [c19]Satoshi Ito, Shigeyuki Nishimura, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu
Stochastic TDC architecture with self-calibration. APCCAS 2010: 1027-1030 - [c18]Koji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, Takenori Tateiwa, Haruo Kobayashi:
Timing skew compensation technique using digital filter with novel linear phase condition. ITC 2010: 334-342
2000 – 2009
- 2009
- [j24]Koji Asami, Takahide Suzuki, Hiroyuki Miyajima, Tetsuya Taura, Haruo Kobayashi:
Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 374-380 (2009) - [j23]Santhos A. Wibowo, Zhang Ting, Masashi Kono, Tetsuya Taura, Yasunori Kobori, Ken-ichi Onda, Haruo Kobayashi:
Analysis of Coupled Inductors for Low-Ripple Fast-Response Buck Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 451-455 (2009) - [j22]Hao San
Cross-Noise-Coupled Architecture of Complex Bandpass DeltaSigmaAD Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 998-1003 (2009) - [j21]Ibuki Mori, Yoshihisa Yamada, Santhos A. Wibowo, Masashi Kono, Haruo Kobayashi, Yukihiro Fujimura, Nobukazu Takai, Toshio Sugiyama, Isao Fukai, Norihisa Onishi, Ichiro Takeda, Jun-Ichi Matsuda:
EMI Reduction by Spread-Spectrum Clocking in Digitally-Controlled DC-DC Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1004-1011 (2009) - [j20]Haruo Kobayashi:
Foreword. IEICE Trans. Electron. 92-C(6): 745-746 (2009) - [c17]Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai, Masao Hotta:
A Time-to-Digital Converter with small circuitry. ASP-DAC 2009: 109-110 - 2008
- [j19]Hao San
Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 965-970 (2008) - [c16]Tomohiko Ogawa, Haruo Kobayashi, Masao Hotta, Yosuke Takahashi, Hao San
SAR ADC algorithm with redundancy. APCCAS 2008: 268-271 - [c15]Akihiro Kanbe, Masato Kaneta, Fuminori Yui, Haruo Kobayashi, Nobukazu Takai, Tatsuhiro Shimura, Hitoshi Hirata, Kentarou Yamagishi:
New architecture for envelope-tracking power amplifier for base station. APCCAS 2008: 296-299 - [c14]Ibuki Mori, Keigo Kimura, Yoshihisa Yamada, Haruo Kobayashi, Yasunori Kobori, Santhos Ario Wibowo, Kazuya Shimizu, Masashi Kono, Hao San
High-resolution DPWM generator for digitally controlled DC-DC converters. APCCAS 2008: 914-917 - [c13]Hajime Konagaya, HaiJun Lin, Hao San
ΔΣAD modulator for low power application. APCCAS 2008: 1232-1235 - [c12]Santhos Ario Wibowo, Zhang Ting, Masashi Kono, Tetsuya Taura, Yasunori Kobori, Haruo Kobayashi:
Analysis of coupled inductors for low-ripple fast-response buck converter. APCCAS 2008: 1860-1863 - [c11]Koji Asami, Hidetaka Suzuki, Hiroyuki Miyajima, Tetsuya Taura, Haruo Kobayashi:
Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity. ATS 2008: 105-110 - 2007
- [j18]Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. 90-C(6): 1181-1188 (2007) - [j17]Takanori Komuro, Shingo Sobukawa, Hiroshi Sakayori, Masashi Kono, Haruo Kobayashi:
Total Harmonic Distortion Measurement System of Electronic Devices up to 100 MHz With Remarkable Sensitivity. IEEE Trans. Instrum. Meas. 56(6): 2360-2368 (2007) - [c10]Hao San
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. ASP-DAC 2007: 96-97 - 2006
- [j16]Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori:
A Practical Analog BIST Cooperated with an LSI Tester. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 465-468 (2006) - [j15]Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 908-915 (2006) - [j14]Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta:
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 916-923 (2006) - 2005
- [j13]Jun Otsuki, Hao San
Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths. IEICE Trans. Electron. 88-C(6): 1290-1294 (2005) - [c9]Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori:
A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI. ISCAS (5) 2005: 4281-4284 - 2004
- [c8]Hao San, Haruo Kobayashi, Shinya Kawakami, Nobuyuki Kuroiwa:
An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators. VLSI Design 2004: 151-156 - 2003
- [j12]Takao Myono, Tatsuya Suzuki, Akira Uemoto, Shuhei Kawai, Takashi Iijima, Nobuyuki Kuroiwa, Haruo Kobayashi:
High-Efficiency Charge-Pump Circuits which Use a 0.5Vdd-Step Pumping Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 371-380 (2003) - [j11]Takayuki Daimon, Hiroshi Sadamura, Takayuki Shindou, Haruo Kobayashi, Masashi Kono, Takao Myono, Tatsuya Suzuki, Shuhei Kawai, Takashi Iijima:
Spread-Spectrum Clocking in Switching Regulators for EMI Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 381-386 (2003) - [j10]Haruo Kobayashi, Hiroshi Yagi, Takanori Komuro, Hiroshi Sakayori:
Algorithms for Digital Correction of ADC Nonlinearity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 504-508 (2003) - 2002
- [j9]Haruo Kobayashi, Kensuke Kobayashi, Masanao Morimura, Yoshitaka Onaya, Yuuich Takahashi, Kouhei Enomoto, Hideyuki Kogure:
Sampling Jitter and Finite Aperture Time Effects in Wideband Data Acquisition Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 335-346 (2002) - [j8]Naoki Kurosawa, Haruo Kobayashi, Kensuke Kobayashi:
Channel Linearity Mismatch Effects in Time-Interleaved ADC Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 749-756 (2002) - [j7]Masaru Kimura, Kensuke Kobayashi, Haruo Kobayashi:
A Quasi-Coherent Sampling Method for Wideband Data Acquisition. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 757-763 (2002) - 2001
- [j6]Haruo Kobayashi, Kensuke Kobayashi, Hiroshi Sakayori, Yasuyuki Kimura:
ADC standard and testing in Japanese industry. Comput. Stand. Interfaces 23(1): 57-64 (2001) - [c7]Naoki Kurosawa, Haruo Kobayashi, Kensuke Kobayashi:
Channel linearity mismatch effects in time-interleaved ADC systems. ISCAS (1) 2001: 420-423
1990 – 1999
- 1999
- [c6]Haruo Kobayashi, Masanao Morimura, Kensuke Kobayashi, Yoshitaka Onaya:
Aperture jitter effects in wideband ADC systems. ICECS 1999: 1705-1708 - [c5]Mohd Asmawi Mohamed Zin, Haruo Kobayashi, Kazuya Kobayashi, Jun-ichi Ichimura, Hao San
A high-speed CMOS track/hold circuit. ICECS 1999: 1709-1712 - [c4]Takao Myono, E. Nishibe, S. Kikuchi, K. Iwatsu, Tatsuya Suzuki, Y. Sasaki, K. Itoh, Haruo Kobayashi:
Modeling and parameter extraction technique for high-voltage MOS device. ISCAS (6) 1999: 230-233 - 1998
- [j5]Tetsuya Yagi, Haruo Kobayashi, Takashi Matsumoto, Koji Tanaka:
Vision chip architecture with light adaptation mechanism. Artif. Life Robotics 2(1): 12-18 (1998) - [c3]Haruo Kobayashi, Takashi Matsumoto:
Spatial and temporal stability of vision chips including parasitic inductances and capacitances. ICASSP 1998: 1081-1084 - [c2]Khayrollah Hadidi, K. Eguchi, Takashi Matsumoto, Haruo Kobayashi:
A highly linear second-order stage for 500-MHz third-order and fifth-order filters. ICECS 1998: 361-364 - 1995
- [j4]Haruo Kobayashi, Takashi Matsumoto, Tetsuya Yagi, Koji Tanaka:
Light-adaptive architectures for regularization vision chips. Neural Networks 8(1): 87-101 (1995) - [j3]Haruo Kobayashi, Takashi Matsumoto, Jun Sanekata:
Two-dimensional spatio-temporal dynamics of analog image processing neural networks. IEEE Trans. Neural Networks 6(5): 1148-1164 (1995) - [c1]Haruo Kobayashi, Hiroshi Sakayori, Tsutomu Tobari, Hiroyuki Matsuura:
Error Correction Algorithm for Folding/Interpolation ADC. ISCAS 1995: 700-703 - 1993
- [j2]Haruo Kobayashi, Takashi Matsumoto, Tetsuya Yagi, Takuji Shimmi:
Image processing regularization filters on layered architecture. Neural Networks 6(3): 327-350 (1993) - 1992
- [j1]Takashi Matsumoto, Haruo Kobayashi, Yoshio Togawa:
Spatial versus temporal stability issues in image processing neuro chips. IEEE Trans. Neural Networks 3(4): 540-569 (1992)
Coauthor Index
[j53] [j52] [c131] [c130] [c129] [j51] [j50] [j49] [j48] [c128] [c127] [c126] [c125] [j47] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [j46] [j45] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [c95] [c94] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [c75]
Jiang-Lin Wei
aka: Jianglin Wei
aka: Jianglin Wei
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