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Commits on Jun 4, 2025

• Update Agilex 5 user clock configuration sequence (#1677) (#1678)

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  madhuriyer

  and

  michael-adler

  authored
  34a8540

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Commits on May 29, 2025

• Mdeckar1/250527 eseries mdk (#1670)

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  mdeckar1

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  a1f77ee

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Commits on May 28, 2025

• Detect missing IP search path when invoking qsys-script (#1672)

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  michael-adler

  authored
  8d4bde2

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• update to Altera (#1671)

  nahidhassan-intel

  authored
  0a7140e

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Commits on May 23, 2025

• Mdeckar1/250522 eseries mdk g3 pld clkfreq user hwtcl (#1668)

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  mdeckar1

  authored
  5070dfd

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Commits on May 7, 2025

• [Update]: Updating static region & pr region for agx5 variant (#1660)

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  madhuriyer

  authored
  3be90b1

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Commits on Apr 25, 2025

• [Fix] make mem_tg work for Agilex 5 MDK (#1657)

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  boelkrug-altera

  authored
  dfb25b4

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Commits on Apr 24, 2025

• Repair ASE compilation (#1659)

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  michael-adler

  authored
  e01d217

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• Move SV wrapper source declaration to a Tcl file (#1658)

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  michael-adler

  authored
  0f8c9f0

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Commits on Apr 22, 2025

• Initial support for DDR4 on Agilex 5 (#1654)

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  michael-adler

  authored
  2e2317a

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Commits on Apr 17, 2025

• Use SystemVerilog wrapper around mem_ss from ip_gen_sv_wrapper.tcl (#1652)

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  michael-adler

  authored
  5ee5cb4

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Commits on Apr 16, 2025

• [Update]: Updating debug flag for modelsim tests (#1650)

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  madhuriyer

  authored
  f674cfd

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Commits on Apr 14, 2025

• Fixing all HSSI MSIM tests (#1648)

  madhuriyer

  authored
  3edd622

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Commits on Apr 7, 2025

• Add support for QSYS projects to SV wrapper generator (#1647)

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  michael-adler

  authored
  4be43a2

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• mem_tg do NOT $finish on axi error (#1644)

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  mdeckar1

  authored
  37466f1

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Commits on Apr 4, 2025

• [Fix]: Fixing failing iseries-dk HSSI modelsim tests (#1645)

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  madhuriyer

  authored
  349038d

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Commits on Apr 1, 2025

• Fixing bad tab spacing in the file (#1642)

  madhuriyer

  authored
  2eea945

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Commits on Mar 31, 2025

• Updating modelsim filelists (#1641)

  madhuriyer

  authored
  1dcf850

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Commits on Mar 19, 2025

• Only process IP files with the new Tcl SV wrapper generator (#1634)

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  michael-adler

  authored
  122a74a

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• Use generic IP wrapper for managing sys_pll (#1633)

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  michael-adler

  authored
  2fcef55

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Commits on Mar 18, 2025

• New SV interface generator around IP (#1632)

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  michael-adler

  authored
  07b21e4

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Commits on Mar 17, 2025

• Fix the HWTCL variable for the number of PCIe segments (#1631)

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  michael-adler

  authored
  12a935a

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• Fix compilation when INCLUDE_HSSI isn't defined (#1629)

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  michael-adler

  authored
  b2753d6

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Commits on Mar 13, 2025

• Update vcsmx setup script for Quartus 25.1 (#1627)

  michael-adler

  authored
  2c92070

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Commits on Mar 10, 2025

• n6001 quartus 25.1 upgrade (#1621)

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  mdeckar1

  and

  madhuriyer

  authored
  a14a0a9

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Commits on Feb 21, 2025

• [Update]: Moving verification folder to env_not_shipped (#1615)

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  madhuriyer

  authored
  97225c3

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Commits on Feb 20, 2025

• updating security and license sdl (#1617)

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  nahidhassan-intel

  authored
  24b6a60

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Commits on Feb 13, 2025

• [Update]: Moving OFS BFM to ofs-common folder (#1614)

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  madhuriyer

  authored
  36627c7

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Commits on Feb 11, 2025

• Configurable Agilex 5 user clock (#1613)

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  michael-adler

  and

  mdeckar1

  authored
  8ea1105

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Commits on Feb 7, 2025

• Mdeckar1/250206 tg2 axi mem (#1611)

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  mdeckar1

  authored
  299ed9f

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Commits on Jan 23, 2025

• Prune board directories in the work tree (#1601)

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  michael-adler

  authored
  d4c989a

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Commits on Jan 21, 2025

• Several updates for Signal Tap in PR regions (#1600)

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  michael-adler

  authored
  19e8361

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Commits on Jan 11, 2025

• Clean up dup_port_rst din (#1593)

  mdeckar1

  authored
  a812f1a

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Commits on Jan 10, 2025

• Update copy engine test with PCIe pin wrapper (#1591)

  michael-adler

  authored
  6709ad2

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Commits on Jan 9, 2025

• fixing endif wrong line (#1587)

  nahidhassan-intel

  authored
  8f5e3b8

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