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Commits on May 17, 2026

• feat(isolated-buck-boost): DAB-quality NRMSE — Fly-Buck-Boost topology fix per TI SNVAA84

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• feat(isolated-buck): DAB-quality NRMSE — K=1 coupling + piecewise primary current

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• feat(pushpull): DAB-quality NRMSE — shape-match OP + 256-shift alignment

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• feat(flyback): DAB-quality NRMSE — snubber DC-bias fix + shape-match OP + CCM check

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Commits on May 16, 2026

• feat(psfb): replace MOSFET-RON freewheel tau with diode-dynamic-R model

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• test(dump): extend WaveformDumpHelpers.h to also emit voltages and Im

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• test: add MKF_DUMP_WAVEFORMS=1 helper for side-by-side analytical-vs-SPICE CSV

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• docs: mark PSHB as DAB-quality in FUTURE_TOPOLOGIES tier table

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• feat(psfb,pshb): physics-derived freewheel decay tau = Lr/(2*RON) — PSHB now DAB-quality

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• fix(psfb,pshb): make diode-drop physically consistent across analytical & SPICE

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• docs(llc): mark LLC rework DONE (Tracks A + B) in FUTURE_TOPOLOGIES

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• feat(llc): Track B — add full-bridge / current-doubler / voltage-doubler rectifier variants

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• feat(llc): rework Track A — DAB-quality polish (ZVS diagnostics, docstring, ITL=500, multi-output warn)

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Commits on May 15, 2026

• feat(cllc): P8b — reverse-mode TDA propagator + reverse PtP NRMSE fixture

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• feat(cllc): P8 — reverse mode SPICE physical (bridge swap) + power-balance test

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• feat(cllc): P7 — asymmetric a/b ratios + half-bridge variant + KIT 20 kW PtP

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• test(cllc): P6 — NRMSE acceptance gates per plan §8

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• feat(cllc): P5 — get_extra_components_inputs (Cr1, Cr2, Lr1, Lr2)

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• feat(cllc): P4 — SPICE rewrite (active SR, snubbers, GEAR, IC, Evab, sense, analytical fallback)

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• feat(cllc): P3 — ZVS margin diagnostics (Infineon AN Eq 28)

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• feat(cllc): P2 — TDA solver, mode/LIP diagnostics, frozen-tank mode test

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• feat(clllc): Phase B-2 — get_extra_components_inputs (Cr1/Cr2 + bus caps + discrete Lr1/Lr2)

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• feat(cllc): P1 — schema v2 wiring + DAB-quality header

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• feat(clllc): Phase B-1 — SPICE netlist + simulate/extract + NRMSE gate

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• feat(clllc): Phase A — analytical 4-state solver (forward + reverse)

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• test(clllc): add regression net for v1 skeleton (helpers, checks, design reqs)

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• test(ahb): add VoltSecondBalance_AllWindings test for all 3 rectifier types

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• fix(clllc): rename Cllllc -> Clllc (typo - one too many L's)

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• fix(magnetic-adviser): preserve ranking spread for single-filter scenarios

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• feat(vienna): add Vienna rectifier - Phase 1+2 (skeleton + analytical)

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Commits on May 14, 2026

• feat(src): Series Resonant Converter (SRC) Phase 1+2 — skeleton + FHA solver

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• fix(magnetic-filter): correct scoring for impedance, saturation, current density

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• fix(magnetic-adviser): clear stale scorings + skip strict filters in score loop

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• M2 Phase 4 (LLC): add VOLTAGE_CONTROLLED_SWITCH bridge mode

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• M2 Phase 3: dual-mode bridge for PSHB + refactor bridge mode out of SpiceSimulationConfig

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