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Commits on Dec 16, 2022

• kc705: support merging rtio and sys clocks

  Spaqin

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Commits on Nov 30, 2022

• kasli: enforce rtiosyscrg config with do_finalize

  

  Spaqin

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  sbourdeauducq

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• 125MHz bootstrap clock, additional false paths

  

  Spaqin

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• kasli: separate bootstrap domain completely

  

  Spaqin

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• kasli: on <2.0 use 62.5MHz bootstrap

  

  Spaqin

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• kasli:

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  Spaqin

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• remove div2 case for rtiosyscrg

  

  Spaqin

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• kasli: minor cosmetics

  

  Spaqin

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• kasli: allow more configuration for rtiosyscrg

  

  Spaqin

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Commits on Oct 10, 2022

• kasli: SYS/RTIO clock merge (#129)

  Spaqin

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Commits on Oct 8, 2022

• fix imports

  sbourdeauducq

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• update version number

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• fix imports

  sbourdeauducq

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• remove more unmaintained code, fix imports

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• README: update

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• remove unmaintained/bitrotten parts. Closes #131

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Commits on Apr 7, 2022

• cpu_interface: use dmb() on ARM to avoid unsupported AXI bursts

  Spaqin

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Commits on Jan 11, 2022

• libunwind: fix warning

  

  occheung

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Commits on Dec 5, 2021

• pass TARGET_AR to Cargo

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Commits on Nov 10, 2021

• update vexriscv-verilog

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• update vexriscv-verilog

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Commits on Nov 9, 2021

• soc_core: revert 4f66420

  

  occheung

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Commits on Nov 8, 2021

• libbase/vexriscv(-g): fix typo

  

  occheung

  authored and

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• soc: define endianness in cpu core

  

  occheung

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• soc_sdram: fix mixxing cpu-type in help text

  

  occheung

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• cpu_type: riscv32g -> vexriscv-g

  

  occheung

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• use soc_core endianness

  

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• soc_core: add endianness attribute

  

  occheung

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• riscv32g: add boot assembly files

  

  occheung

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• libunwind: add CPU name to -elf unwinder

  

  occheung

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• update vexriscv-verilog

  

  occheung

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• soc_core: add cpu_bus_width arg

  

  occheung

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• sdram: add cpu_bus_width arg

  

  occheung

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• builder: compilation with multiple cpu type

  

  occheung

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• libunwind: generate unwinder for hard-float kernel

  

  occheung

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