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    153 repositories

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •951•3.1k•1.5k•347•Updated Feb 10, 2026Feb 10, 2026

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      hardwarerisc-vrv32cpucore
      SystemVerilog
      •
      Apache License 2.0
      •685•1.8k•213•40•Updated Feb 10, 2026Feb 10, 2026

    • lowrisc-nix

      Public
      lowRISC Nix Packages and Environments
      Nix
      •
      MIT License
      •10•7•1•1•Updated Feb 10, 2026Feb 10, 2026

    • dvsim

      Public
      DVSim is a build and run system written in Python that runs a variety of EDA tool flows
      Python
      •
      Apache License 2.0
      •8•5•23•3•Updated Feb 9, 2026Feb 9, 2026

    • opentitan-provisioning

      Public
      Reference OpenTitan Provisioning Infrastructure
      Go
      •
      Apache License 2.0
      •10•12•14•1•Updated Feb 6, 2026Feb 6, 2026

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      SystemVerilog
      •
      Other
      •750•0•0•0•Updated Feb 6, 2026Feb 6, 2026

    • lowrisc-toolchains

      Public
      UNSUPPORTED INTERNAL toolchain builds
      Shell
      •21•47•3•1•Updated Feb 4, 2026Feb 4, 2026

    • qemu

      Public
      Fork of QEMU for development of lowRISC platforms (including OpenTitan)
      C
      •
      Other
      •6.5k•6•12•2•Updated Feb 4, 2026Feb 4, 2026

    • sonata-software

      Public
      Software, build flows and examples for the Sonata System
      C++
      •
      Apache License 2.0
      •16•13•3•0•Updated Jan 23, 2026Jan 23, 2026

    • ibex-demo-system

      Public
      A demo system for Ibex including debug support and some peripherals
      C
      •
      Apache License 2.0
      •72•85•13•7•Updated Jan 21, 2026Jan 21, 2026

    • benevisrdl

      Public
      This repository houses PeakRDL plugins, named after Ben Nevis, the UK's tallest peak.
      SystemVerilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Jan 7, 2026Jan 7, 2026

    • llvm-project

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this …
      C++
      •16k•2•0•0•Updated Jan 6, 2026Jan 6, 2026

    • sonata-system

      Public
      A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
      C++
      •
      Apache License 2.0
      •31•46•14•9•Updated Dec 11, 2025Dec 11, 2025

    • sail

      Public
      Sail architecture definition language
      Isabelle
      •
      Other
      •146•0•0•0•Updated Dec 3, 2025Dec 3, 2025

    • binutils

      Public
      (Unsupported) lowRISC fork of Binutils
      C
      •
      GNU General Public License v2.0
      •1•0•0•1•Updated Nov 26, 2025Nov 26, 2025

    • container-hotplug

      Public
      Hot-plug devices into a Docker container as they are plugged.
      Rust
      •5•15•2•0•Updated Nov 18, 2025Nov 18, 2025

    • style-guides

      Public
      lowRISC Style Guides
      Creative Commons Attribution 4.0 International
      •128•477•19•1•Updated Nov 6, 2025Nov 6, 2025

    • ot-sca

      Public
      Side-channel analysis setup for OpenTitan
      Jupyter Notebook
      •
      Apache License 2.0
      •33•37•27•5•Updated Nov 3, 2025Nov 3, 2025

    • serde-annotate

      Public
      Serde Serializer with formatting controls
      Rust
      •
      Apache License 2.0
      •5•1•0•0•Updated Oct 16, 2025Oct 16, 2025

    • QuickCheckVEngine

      Public
      A RISC-V TestRIG Verification Engine based on QuickCheck
      Haskell
      •
      BSD 2-Clause "Simplified" License
      •11•0•0•0•Updated Sep 4, 2025Sep 4, 2025

    • cheriot-ibex

      Public
      cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
      SystemVerilog
      •
      Apache License 2.0
      •25•1•0•0•Updated Aug 21, 2025Aug 21, 2025

    • TestRIG

      Public
      Testing processors with Random Instruction Generation
      Python
      •
      Other
      •17•1•0•0•Updated Aug 13, 2025Aug 13, 2025

    • sail-cheri-riscv

      Public
      CHERI-RISC-V model written in Sail
      Isabelle
      •
      Other
      •25•0•0•0•Updated Jul 10, 2025Jul 10, 2025

    • parallel-cp

      Public
      A tiny parallel file copy utility
      Rust
      •0•1•0•0•Updated Jul 4, 2025Jul 4, 2025

    • cheriot-sail

      Public
      Sail code model of the CHERIoT ISA
      TeX
      •
      Other
      •17•1•0•0•Updated Jul 1, 2025Jul 1, 2025

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •245•0•0•0•Updated Jul 1, 2025Jul 1, 2025

    • riscv-isa-sim

      Public
      RISC-V Functional ISA Simulator
      C
      •
      Other
      •1k•20•0•2•Updated Jun 20, 2025Jun 20, 2025

    • sunburst-chip

      Public
      An open silicon CHERIoT Ibex microcontroller chip
      C
      •
      Apache License 2.0
      •4•18•6•2•Updated May 23, 2025May 23, 2025

    • rules_python

      Public
      Bazel Python Rules
      Starlark
      •
      Apache License 2.0
      •662•0•0•0•Updated Apr 30, 2025Apr 30, 2025

    • muntjac

      Public
      64-bit multicore Linux-capable RISC-V processor
      SystemVerilog
      •
      Apache License 2.0
      •13•105•1•0•Updated Apr 28, 2025Apr 28, 2025