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fix: Update x86/6.1 MSR baselines with RFDS_NO #4537

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merged 3 commits into from
Apr 3, 2024

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roypat
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@roypat roypat commented Apr 3, 2024

Changes

Since Amazon Linux commit
amazonlinux/linux@b2e92ab, KVM passes through bit 27 of the MSR_IA32_ARCH_CAPABILITIES MSR (0x10A) to the guest, to let them know whether the processor they're running on is affected by RFDS. According to Intel, only Atom processors are affected [1], and accordingly, for all instances in our CI this bit is reported to be 1. Thus, update the baselines.

Reason

integration_tests/functional/test_cpu_template_helper.py::test_guest_cpu_config_change failing on x86/6.1

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PR Checklist

  • If a specific issue led to this PR, this PR closes the issue.
  • The description of changes is clear and encompassing.
  • Any required documentation changes (code and docs) are included in this
    PR.
  • API changes follow the Runbook for Firecracker API changes.
  • User-facing changes are mentioned in CHANGELOG.md.
  • All added/changed functionality is tested.
  • New TODOs link to an issue.
  • Commits meet
    contribution quality standards.

  • This functionality cannot be added in rust-vmm.

@roypat roypat added the Status: Awaiting review Indicates that a pull request is ready to be reviewed label Apr 3, 2024
@zulinx86
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zulinx86 commented Apr 3, 2024

Could you please also update CPU templates with CHANGELOG?

  • T2CL: passthrough the bit (like a628a18)
  • T2S: set the bit (like 7b62670)

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codecov bot commented Apr 3, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 82.03%. Comparing base (4992bf3) to head (014a6aa).

Additional details and impacted files
@@           Coverage Diff           @@
##             main    #4537   +/-   ##
=======================================
  Coverage   82.02%   82.03%           
=======================================
  Files         253      253           
  Lines       31046    31048    +2     
=======================================
+ Hits        25467    25469    +2     
  Misses       5579     5579           
Flag Coverage Δ
4.14-c5n.metal 79.49% <100.00%> (+<0.01%) ⬆️
4.14-c7g.metal ?
4.14-m5n.metal 79.48% <100.00%> (+<0.01%) ⬆️
4.14-m6a.metal 78.69% <ø> (+<0.01%) ⬆️
4.14-m6g.metal 76.67% <ø> (ø)
4.14-m6i.metal 79.47% <100.00%> (-0.01%) ⬇️
4.14-m7g.metal 76.67% <ø> (?)
5.10-c5n.metal 82.03% <100.00%> (+<0.01%) ⬆️
5.10-c7g.metal ?
5.10-m5n.metal 82.02% <100.00%> (+<0.01%) ⬆️
5.10-m6a.metal 81.32% <ø> (+<0.01%) ⬆️
5.10-m6g.metal 79.44% <ø> (ø)
5.10-m6i.metal 82.01% <100.00%> (-0.01%) ⬇️
5.10-m7g.metal 79.44% <ø> (?)
6.1-c5n.metal 82.03% <100.00%> (+<0.01%) ⬆️
6.1-m5n.metal 82.02% <100.00%> (+<0.01%) ⬆️
6.1-m6a.metal 81.31% <ø> (ø)
6.1-m6g.metal 79.44% <ø> (ø)
6.1-m6i.metal 82.01% <100.00%> (+<0.01%) ⬆️
6.1-m7g.metal 79.44% <ø> (?)

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@roypat
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roypat commented Apr 3, 2024

Could you please also update CPU templates with CHANGELOG?

* T2CL: passthrough the bit (like [a628a18](https://github.com/firecracker-microvm/firecracker/commit/a628a18558de3b087baffc7ec6d1244872353cb2))

* T2S: set the bit (like [7b62670](https://github.com/firecracker-microvm/firecracker/commit/7b62670ece70c9e9dfb80050eee272fc51cd65ff))

Done, thanks!

Since Amazon Linux commit
amazonlinux/linux/b2e92ab17e440a97c716b701ecd897eebca11ac0,
KVM passes through bit 27 of the `MSR_IA32_ARCH_CAPABILITIES` MSR
(0x10A) to the guest, to let them know whether the processor they're
running on is affected by RFDS. According to Intel, only Atom processors
are affected [[1]], and accordingly, for all instances in our CI this
bit is reported to be 1. Thus, update the baselines.

[1]: https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/register-file-data-sampling.html

Signed-off-by: Patrick Roy <roypat@amazon.co.uk>
Passthrough in T2CL template, set to 1 in T2S template.

Signed-off-by: Patrick Roy <roypat@amazon.co.uk>
@roypat roypat merged commit 21a3a6d into firecracker-microvm:main Apr 3, 2024
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4 participants