library IEEE;
use IEEE.std_logic_1164.all;

entity naming is
        generic (
                do_sub : boolean := FALSE
        );
        port (
                din  : in    std_logic;
                clk  : in    std_logic;
                dout :   out std_logic
        );
end entity;

architecture bug of naming is
        component ff is
                port (
                        din  : in    std_logic;
                        clk  : in    std_logic;
                        dout :   out std_logic
                );
        end component;

        signal sub : std_logic := '0';
        signal res : std_logic := '0';

begin

        g_sub: if do_sub generate

                inst : ff
                        port map (
                                din => din,
                                clk => clk,
                                dout => sub
                        );

        end generate;

        inst : ff
                port map (
                        din => din,
                        clk => clk,
                        dout => res
                );

        dout <= res xor sub;

end architecture;