Partial reconfiguration example using FMCOMMS2 with a Xilinx FPGA.

This tag point to the old development branch, the time when

there were just two branches: master and dev.

This commit(s) are using the hdl_2018_r1 realeas as its base.

It's an exemple how to use a clock domain crossing FIFO in the
receive path, to have a 100MHz clock rate for further processing.

A FIR filter integration example for FMCOMMS2.

This commit(s) contains an example design for the ADRV9371x

project, when a 3-wire SPI is used to configure the device.
The example design is using the hdl_2018_r1 release branch as its
base.

Tag for the 2018_r1 release

The following deprecated porjects can be found here:

  * ADRV9361Z7035_ccpci_lvds

  * ADRV9361Z7035_ccusb_lvds

  * ADRV9364Z7020_ccusb_lvds

  * ADRV7511 with VC707, KC705 and KCU105

axi_logic_analyzer: Fix push-pull/open-drain selection

library: Delete all adi_ip_constraint process call

daq2/kcu105- intc configurations