Highlights
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iverilog Public
Forked from steveicarus/iverilogIcarus Verilog
C++ GNU Lesser General Public License v2.1 UpdatedMay 19, 2020 -
bsg_fakeram Public
Forked from bespoke-silicon-group/bsg_fakeramfakeram generator for use by researchers who do not have access to commercial ram generators
Python BSD 3-Clause "New" or "Revised" License UpdatedMar 17, 2020 -
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open-src-cvc Public
Forked from cambridgehackers/open-src-cvcMirror of tachyon-da cvc Verilog simulator
C UpdatedMar 4, 2020 -
PySpice Public
Forked from PySpice-org/PySpiceSimulate electronic circuit using Python and the Ngspice / Xyce simulators
Python GNU General Public License v3.0 UpdatedFeb 28, 2020 -
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AutoCkt Public
Forked from ksettaluri6/AutoCktDeep Reinforcement Learning of Analog Circuit Designs
Python UpdatedJan 31, 2020 -
MAGICAL Public
Forked from magical-eda/MAGICALMachine Generated Analog IC Layout
C++ BSD 3-Clause "New" or "Revised" License UpdatedJan 30, 2020 -
ALIGN-public Public
Forked from ALIGN-analoglayout/ALIGN-publicC++ BSD 3-Clause "New" or "Revised" License UpdatedJan 29, 2020 -
riscv-formal Public
Forked from SymbioticEDA/riscv-formalRISC-V Formal Verification Framework
Verilog ISC License UpdatedJan 20, 2020 -
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osu_soc Public
Standard cell libraries from Oklahoma State University
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doxymacs Public
Forked from pniedzielski/doxymacsDoxymacs is Doxygen + {X}Emacs.
Emacs Lisp GNU General Public License v3.0 UpdatedApr 16, 2019 -
verilog_sim_utils Public
Various verilog files to help writting testbenches
Verilog UpdatedMar 11, 2019 -
darkriscv Public
Forked from darklife/darkriscvopensouce RISC-V implemented from scratch in one night!
Verilog BSD 3-Clause "New" or "Revised" License UpdatedFeb 28, 2019 -
vcdvcd Public
Forked from cirosantilli/vcdvcdPython Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line viewer.
Python Other UpdatedJan 5, 2019 -
arty-cm0-designstart Public
A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
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py3antlr4book Public
Forked from jszheng/py3antlr4bookCovert ANTLR4 book source code to Python3 version.
Python UpdatedAug 22, 2018 -
grammars-v4 Public
Forked from antlr/grammars-v4Grammars written for ANTLR v4; expectation that the grammars are free of actions.
ANTLR UpdatedAug 22, 2018 -
Pyverilog Public
Forked from PyHDI/PyverilogPython-based Hardware Design Processing Toolkit for Verilog HDL
Python Other UpdatedAug 21, 2018 -
pyverilog-test Public
Tests for the pyverilog Verilog parser
Makefile MIT License UpdatedAug 21, 2018 -
apb-bridge Public
An APB bridge and mux generator based on the junctions/Poci chisel code
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prelude Public
Forked from bbatsov/preludeLocal copy of Emacs prelude to keep track of local setup
Emacs Lisp UpdatedMay 6, 2018 -
adv_debug_sys Public
Forked from freecores/adv_debug_sysAdvanced Debug System
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cocotb Public
Forked from cocotb/cocotbCoroutine Co-simulation Test Bench
Python Other UpdatedOct 9, 2017 -
ml-ahb-gen Public
A Verilog AMBA AHB Multilayer interconnect generator