A modern hardware definition language and toolchain based on Python

Python Tool for UVM Testbench Generation

A High-performance Timing Analysis Tool for VLSI Systems

Xilinx Embedded Software (embeddedsw) Development

SystemVerilog support in VS Code

automatic-verilog based on vimscript

SystemVerilog language server

The sources of the online SpinalHDL doc

Digital Design with Chisel

SystemVerilog linter

CNN accelerator implemented with Spinal HDL

Verilog AXI components for FPGA implementation

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Digital timing diagram editor

ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set

Flexible Intermediate Representation for RTL

Verilog VPI module to dump FST (Fast Signal Trace) databases

This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for EDA.

Lab exercises for Chisel in the digital electronics 2 course at DTU

TL Serdes

🥔 MOS-6502 and NES emulator in Rust (SDL/WebAssembly/Android/Embedded/Cloud)

Rocket Chip Generator

synthesiseable ieee 754 floating point library in verilog

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

Chisel: A Modern Hardware Design Language

Open source FPGA-based NIC and platform for in-network compute

Generator Bootcamp Material: Learn Chisel the Right Way