ips
16-bit Adder Multiplier hardware on Digilent Basys 3
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …
Implementing Different Adder Structures in Verilog
Parameterized Booth Multiplier in Verilog 2001
IEEE 754 single and double precision floating point library in systemverilog and vhdl
synthesiseable ieee 754 floating point library in verilog
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their internal components in Verilog
Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Verilog AXI components for FPGA implementation
Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
A CPU cache simulator written in Python
vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)
SPIR-V fragment shader GPU core based on RISC-V
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated