CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

4 stage, in-order, compute RISC-V core based on the CV32E40P

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SonicBOOM: The Berkeley Out-of-Order Machine

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Berkeley's Spatial Array Generator

Hammer: Highly Agile Masks Made Effortlessly from RTL

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Simple RISC-V 3-stage Pipeline in Chisel

Tile based architecture designed for computing efficiency, scalability and generality

SPIR-V fragment shader GPU core based on RISC-V

Rocket Chip Generator

The Ultra-Low Power RISC-V Core

VeeR EH1 core

Icarus Verilog

Open-source high-performance RISC-V processor