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⚠️ simplify CFU interface Verilog Conversion #219: Pull request #1524 synchronize by stnolting
6m 54s cfu_interface
cfu_interface
6m 54s
⚠️ simplify CFU interface Verilog Conversion #218: Pull request #1524 opened by stnolting
7m 5s cfu_interface
cfu_interface
7m 5s
🧪 rework intrinsics (use .insn) (#1523) Verilog Conversion #217: Commit f470fb3 pushed by stnolting
7m 5s main
main
7m 5s
🧪 rework intrinsics (use .insn) Verilog Conversion #216: Pull request #1523 synchronize by stnolting
7m 5s intrinsics_rework
intrinsics_rework
7m 5s
[lsu] add unaligned support Verilog Conversion #215: Pull request #1521 synchronize by bewimm
7m 4s bewimm:add_zicclsm
bewimm:add_zicclsm
7m 4s
[lsu] add unaligned support Verilog Conversion #214: Pull request #1521 synchronize by bewimm
Action required bewimm:add_zicclsm
bewimm:add_zicclsm
Action required
[lsu] add unaligned support Verilog Conversion #213: Pull request #1521 synchronize by bewimm
Action required bewimm:add_zicclsm
bewimm:add_zicclsm
Action required
[lsu] add unaligned support Verilog Conversion #212: Pull request #1521 opened by bewimm
Action required bewimm:add_zicclsm
bewimm:add_zicclsm
Action required
✨ [cache] add write-back & write-allocate policies (#1513) Verilog Conversion #211: Commit 754a093 pushed by stnolting
6m 59s main
main
6m 59s
✨ [cache] add write-back & write-allocate policies Verilog Conversion #210: Pull request #1513 synchronize by stnolting
7m 19s cache_writeback_dev
cache_writeback_dev
7m 19s
[bus_explorer] fix string buffer size Verilog Conversion #209: Commit c51f8ae pushed by stnolting
6m 50s main
main
6m 50s
✨ [cache] add write-back & write-allocate policies Verilog Conversion #208: Pull request #1513 synchronize by stnolting
7m 5s cache_writeback_dev
cache_writeback_dev
7m 5s
✨ [cache] add write-back & write-allocate policies Verilog Conversion #207: Pull request #1513 synchronize by stnolting
6m 50s cache_writeback_dev
cache_writeback_dev
6m 50s
✨ [cache] add write-back & write-allocate policies Verilog Conversion #206: Pull request #1513 synchronize by stnolting
6m 58s cache_writeback_dev
cache_writeback_dev
6m 58s
🚀 preparing release v1.12.9 Verilog Conversion #205: Commit 0efeab3 pushed by stnolting
6m 47s main
main
6m 47s
fix(bus): SC.W returns 0 on success instead of stale memory data (#1520) Verilog Conversion #204: Commit 0ba64e3 pushed by stnolting
6m 52s main
main
6m 52s
fix(bus): SC.W returns 0 on success instead of stale memory data Verilog Conversion #203: Pull request #1520 synchronize by stnolting
6m 54s 14sea:fix/sc-return-value
14sea:fix/sc-return-value
6m 54s
fix(bus): SC.W returns 0 on success instead of stale memory data Verilog Conversion #202: Pull request #1520 opened by 14sea
6m 51s 14sea:fix/sc-return-value
14sea:fix/sc-return-value
6m 51s
✨ [cache] add write-back & write-allocate policies Verilog Conversion #201: Pull request #1513 synchronize by stnolting
7m 6s cache_writeback_dev
cache_writeback_dev
7m 6s
[trng] add TRNG architecture configuration generics and ⚠️ rework con… Verilog Conversion #200: Commit cb8e809 pushed by stnolting
6m 53s main
main
6m 53s
[trng] add TRNG architecture configuration generics and ⚠️ rework control register layout Verilog Conversion #199: Pull request #1518 synchronize by stnolting
6m 54s trng_config
trng_config
6m 54s
[trng] add TRNG architecture configuration generics and ⚠️ rework control register layout Verilog Conversion #198: Pull request #1518 opened by stnolting
7m 5s trng_config
trng_config
7m 5s
[gpio] add optional IO direction control (#1517) Verilog Conversion #197: Commit 416b6bf pushed by stnolting
6m 55s main
main
6m 55s
[gpio] add optional IO direction control Verilog Conversion #196: Pull request #1517 synchronize by stnolting
6m 55s gpio_bidirectional
gpio_bidirectional
6m 55s
[gpio] add optional IO direction control Verilog Conversion #195: Pull request #1517 opened by stnolting
6m 58s gpio_bidirectional
gpio_bidirectional
6m 58s