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Commits on Jul 30, 2021

• Bump version

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Commits on Jul 29, 2021

• opt_lut: Allow more than one -dlogic per cell type.

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  wanda-phi

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• verilog: save and restore overwritten macro arguments

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• Bump version

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Commits on Jul 28, 2021

• verilog: Emit $meminit_v2 cell.

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• backends/verilog: Support meminit with mask.

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• memory: Introduce $meminit_v2 cell, with EN input.

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• Bump version

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Commits on Jul 27, 2021

• proc: Run opt_expr at the end

  wanda-phi

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• opt_expr: Propagate constants to port connections.

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• Bump version

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Commits on Jul 26, 2021

• Add version bump workflow

  mmicko

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Commits on Jul 21, 2021

• Update to latest verific

  mmicko

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Commits on Jul 20, 2021

• Use new read_id_num helper function elsewhere in hierarchy.cc

  

  rswarbrick

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  zachjs

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• Extract connection checking logic from expand_module in hierarchy.cc

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  rswarbrick

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  zachjs

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• Merge pull request #2885 from whitequark/cxxrtl-fix-2883

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  whitequark

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• Merge pull request #2884 from whitequark/cxxrtl-fix-2882

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• cxxrtl: treat wires with multiple defs as not inlinable.

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• cxxrtl: treat assignable internal wires used only for debug as locals.

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• Merge pull request #2881 from whitequark/cxxrtl-sideways-colon

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Commits on Jul 19, 2021

• cxxrtl: escape colon in variable names in VCD writer.

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  whitequark

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Commits on Jul 18, 2021

• Merge pull request #2880 from whitequark/cxxrtl-fix-2877

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• cxxrtl: add debug_item::{get,set}.

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  whitequark

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Commits on Jul 17, 2021

• Merge pull request #2879 from whitequark/cxxrtl-fix-2739-again

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  whitequark

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• cxxrtl: treat internal wires used only for debug as constants.

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Commits on Jul 16, 2021

• Add support for parsing the SystemVerilog 'bind' construct

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  rswarbrick

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  zachjs

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• Merge pull request #2874 from whitequark/cxxrtl-fix-2589

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  whitequark

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• Merge pull request #2873 from whitequark/cxxrtl-fix-2500

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• Merge pull request #2872 from whitequark/cxxrtl-fix-2521

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• cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.

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  whitequark

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• cxxrtl: emit debug items for unused public wires.

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  whitequark

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• cxxrtl: don't expect user cell inputs to be wires.

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• Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841

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  whitequark

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• cxxrtl: don't mark buffered internal wires as UNUSED for debug.

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  whitequark

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• Merge pull request #2870 from whitequark/cxxrtl-fix-2739

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