Stars
Next-Generation AI-Assisted Kernel Engineering for Multi-Chip Systems
FlagGems is an operator library for large language models implemented in the Triton Language.
Open-source AI acceleration on FPGA: from ONNX to RTL
Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other things.
High-performance eBPF implementation in hardware.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
PCI Express DIY hacking toolkit for Xilinx SP605
HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/
Source code for 'Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL' by James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, Xin…
A Python toolbox for building complex digital hardware
Basic ECP5 based GigE to SYZYGY interface.
Provides Spatial with front-end support from popular machine learning frameworks
First lesson for you to use DNNDK, also it can be helpful for your AI learning
implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
Centaur, a framework for hybrid CPU-FPGA databases
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
A network stack implementation for xv6 OS
Automatically exported from code.google.com/p/xv6plus
Disseminated, Distributed OS for Hardware Resource Disaggregation. USENIX OSDI 2018 Best Paper.
HLS-based Xilinx ICAP3 Controller (tested with VCU108)
Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.
This repository contains my small solutions related to HDL design.