Integration of
Novel 3D Structured Devices
BeSang Inc.
3D Enabling Technology
BeSang Inc. Page 1 - Nov. 2007
About BeSang Inc.
A fabless semiconductor IP company
Providing single chip 3D enabling technology to allow large block
of array (i.e. memory array, photo diode, and etc) to be placed
on top of the CMOS circuitry in wafer level.
Implemented its first prototype at Stanford NanoFab in 2006
Operations at Portland, OR, Stanford, CA, & Daejeon, Korea
HQ at Portland, OR Stanford NanoFab National NanoFab Center
BeSang Inc. Page 2 - Nov. 2007
About BeSang’s 3D Technology
BeSang Inc. Page 3 - Nov. 2007
SGT
(Surrounding Gate Transistor)
Advantages & Limitations & Solution
BeSang Inc.
3D Enabling Technology
BeSang Inc. Page 4 - Nov. 2007
SGT Memories
NOR Flash - Sharp NAND Flash -Toshiba DRAM - IBM
DRAM - Infineon SRAM – T-RAM SRAM - Hitachi
BeSang Inc. Page 5 - Nov. 2007
SGT – Ideal Device Structure
Planar Flash Cell 6x more
charge storage
F
F
n+ n+
p n+
p 2F
• Channel has no litho dependence
• Low S/D leakage
• Large driving currents n+
• Low SER (Soft Error Rate)
SGT Flash Cell
BeSang Inc. Page 6 - Nov. 2007
Limitations of SGT Memories
• SGT is not such small
compared to conventional planar
memory devices
Device Type Normalized Size
NOR Flash 8 F2
NAND Flash 4 F2
• Process Incompatibility DRAM 6-8 F2
between memory and logic SGT 4-5 F2
• Gate oxide quality
varies depending
on crystalline
orientation
• High gate overlap capacitance
BeSang Inc. Page 7 - Nov. 2007
Optimized & Compatible Process
&
Embedded
DRAM
Flash
BeSang Inc. Page 8 - Nov. 2007
Manufacturing Cost Reduction
Optimized process for both memory array and control logic
&
10 Masks 20 Masks Limited Extra Masks
3 masks with 90nm
Memory
Total 23 masks
Memory Logic
Fast & Optimized Logic
Logic 20 masks with 0.13 um
Old generation litho tool is
90 nm 0.3 um BeSang’s good enough for 0.13 um
3D Chip logic wafer processing: tool
For NAND Flash & mask investment savings
Total 30 masks
BeSang Inc. Page 9 - Nov. 2007
Technology & Process Flow
BeSang Inc.
3D Enabling Technology
BeSang Inc. Page 10 - Nov. 2007
Process Flow - 1
STEP 1: Conventional CMOS Wafer
Interconnect
Semiconductor Substrate 1
CMOS
Semiconductor Substrate 1 circuitry
STEP 2: Donor Wafer
Doping
n+
p
n+
Semiconductor Substrate 2 Semiconductor Substrate 2
BeSang Inc. Page 11 - Nov. 2007
Process Flow - 2
STEP 3: Wafer Bonding & Detaching Semiconductor Substrate 2
n+
p
Semiconductor Substrate 2
n+
Semiconductor Substrate 1
CMOS
Semiconductor Substrate 1 circuitry
No Wafer Alignment is Needed
STEP 4: Thin Silicon Layer on Top of CMOS Circuitry
Thin silicon layer with impurity doping
Interconnect
Semiconductor Substrate 1
CMOS
Semiconductor Substrate 1 circuitry
BeSang Inc. Page 12 - Nov. 2007
Thin Silicon Layer
On Top of CMOS Circuitry
BeSang A Company
Very Good Many Defects
Low temperature bonding and detaching.
BeSang Inc. Page 13 - Nov. 2007
Thin Silicon Layer
On Top of CMOS Circuitry
Cross-Sectional View
Semiconductor Substrate 1
Wafer bonding strength is exceptional!
BeSang Inc. Page 14 - Nov. 2007
Process Flow – 3
Standard CMOS Tools & Process
STEP 5: Silicon Etching n+
p
n+
Semiconductor Substrate 1
CMOS
Semiconductor Substrate 1 circuitry
STEP 6: Gate & Connections
Vertical
memory
Semiconductor Substrate 1
CMOS
Semiconductor Substrate 1 circuitry
No High Temperature Process is Needed
BeSang Inc. Page 15 - Nov. 2007
Gate Formation
Gate Silicon Pillar 3-4 extra masks are good enough to
implement vertical memories.
Semiconductor Substrate 1
Vertical
memory
BeSang Inc.
CMOS
Top View Semiconductor Substrate 1
circuitry
No need to develop logic wafer (reuse Cross-Sectional View
conventional CMOS logic process) –
Fast R&D
BeSang Inc. Page 16 - Nov. 2007
BeSang’s 3D IC vs. 3D Packages
BeSang’s Single Conventional 3D Hybrid
Item
Chip 3D Package 3D Package
Die Cost Low Normal High
Speed High Slow Medium
Embedded Memory
Yes No No
Solution
High Density
Yes No No
Memory Solution
Precise Alignment NO Yes Yes
Interconnects Unlimited Few 100s Few 1,000s
BeSang Inc. Page 17 - Nov. 2007
Summary of Process Flow
• Special Tools
NO! • New Material
• New Device Concept
• Extra Masks
Limited • Process Steps
• Cost Increment
BeSang technology can be processed at conventional CMOS fabs
BeSang Inc. Page 18 - Nov. 2007
Device Characteristics & Reliability
BeSang Inc.
3D Enabling Technology
BeSang Inc. Page 19 - Nov. 2007
From Stanford NanoFab
Program/Erase – 140 times Endurance Window
0.6
1.50E-04 0.5
0.4
0.3
Id (A)
1.00E-04
V th (V )
Vth after
0.2 Erasing
Vth after
Programming
0.1
5.00E-05
0
-0.1
1 10 100 1000 10000 100000
0.00E+00
# of P/E Cycle
-1 0 1 2 3
Vg (V)
2.00E-04
Multi-bit
1.50E-04 Program
Id (A)
1.00E-04
5.00E-05 Multi-bit Program
0.00E+00
0 1 2 3 4 5
Vg (V) Gate Leakage
BeSang Inc. Page 20 - Nov. 2007
1Gb Flash Test Chip Design
Experiment for expension capability
128 million SGTs Number of Cells: 128 millions
x 2 with multi bit (or multi level)
x 2 with double stacked SGT
x 2 with double memory layers
1M SGTs = 1Gb Memory
Feature Size 0.18 um 90 nm 60 nm
Pillar Size 0.2 um 0.1 um 70 nm
Pillar Space 0.3 um 0.15 um 110 nm Space for
Space for 3D Wiring 3.0 um 1.5 um 1.0 um 3D wiring
1Mb 0.0296 0.0074 0.0037
1Gb 29.57 7.39 3.70
B/L
16Gb 118 59
64Gb 237 W/L
NOTE: Chip size (mm2) excluding pad area
BeSang Inc. Page 21 - Nov. 2007
na l
ti o
v en
Con
Problems with CMOS
BeSang Inc.
3D Enabling Technology
BeSang Inc. Page 22 - Nov. 2007
Memory Core is #1 Functional Block
in Memory, CPU, and SoC devices
DRAM
Flash
SRAM
Embedded
Embedded DRAM
SRAM
Embedded
Flash
Embedded
DRAM
BeSang Inc. Page 23 - Nov. 2007
Memory is NOT Affordable
•SoCs are 'dead,' Intel manager declares By David Lammers EE Times, February 12, 2003, “The
system-on-chip movement is "dead," ambushed by the cost of additional mask layers needed to
marry digital logic with memory and analog functions, Intel Corp. architecture manager Jay Heeb
told the International Solid-State Circuits Conference on Tuesday.”
•Embedded DRAM Market by Instat/MDR, 5/7/2002 “While embedded DRAM technology has been
available for nearly a decade, it has never reached the level of revenues originally forecast by many
industry analysts. In large part, it faces the same issue as the flash memory market - incompatibility
between conventional memory and standard logic wafer processes. Even though these issues will be
addressed and resolved in the future, density limitations within a system-level design will remain a
major restriction.”
BeSang Inc. Page 24 - Nov. 2007
Low Cost Memory through BeSang’s 3D
More Die per Wafer
Memory
Core
Peri-
Memory Core
Logic
Peri-
Cross-Section of Logic
a conventional Chip
Cross-Section of a 3D Chip
Chip Layout of a Chip Layout of a 3D Wafer
conventional Wafer
BeSang Inc. Page 25 - Nov. 2007
Multi-Billion Dollar Fab Investment Savings
Big fab is efficient, but expensive
300 mm Fab
Source: Goldman Sacks
• $2~$3 billion investment
• 1.3x wafer cost
• 2.5x more die
3D fab is more efficient, and affordable
Conventional Fab 3D Fab
• $10~$20 million investment
• 1.2x wafer cost
• 2x-5x more die
BeSang Inc. Page 26 - Nov. 2007
Summary
BeSang Inc.
3D Enabling Technology
BeSang Inc. Page 27 - Nov. 2007
BeSang’s Solution
“Single Chip” 3D Technology
Unlimited conventional vias connect memory layer on top of logic circuitry
seamlessly, which enables high density “Memory Core” solutions.
High density cells
Small die size
Few process steps
BeSang Inc. Page 28 - Nov. 2007
Benefits of BeSang 3D Technology
Dramatic
cell size reduction
5 times more chips per wafer
Item Conventional 2D IC BeSang’s 3D IC
Relative Chip Cost 100 % 20 %
Relative Time-to-Market Present 2 generation ahead
Time for R&D 6 years 1 years
Fab Investment Cost ~ 3 billion ~ 100 million
BeSang Inc. Page 29 - Nov. 2007
Acknowledgement
9 Prof. Yoshio Nishi for his advice and guidance on BeSang’s 3D
technology development
9 Stanford NanoFab, Mr. Paul Rissman, and staffs for their
strong support
9 Tokyo Electron for direct support for Trias-SPA processing
9 National NanoFab Center for 8 inch & 0.18 um technology
development
BeSang Inc. Page 30 - Nov. 2007
