See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/4060235

Advanced topics of DFT technologies in a general purposed CPU chip

Conference Paper · November 2003

DOI: 10.1109/ICASIC.2003.1277424 · Source: IEEE Xplore

CITATIONS READS

3 150

6 authors, including:

Yong-Jun Xu Tao Lv
Chinese Academy of Sciences Chinese Academy of Sciences
95 PUBLICATIONS   770 CITATIONS    22 PUBLICATIONS   114 CITATIONS   

SEE PROFILE SEE PROFILE

Huawei Li Xiao-Wei Li
Chinese Academy of Sciences Chinese Academy of Sciences
196 PUBLICATIONS   1,153 CITATIONS    272 PUBLICATIONS   2,018 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

Energy-Efficient Architecture View project

Error Tolerant Computing View project

All content following this page was uploaded by Huawei Li on 30 May 2014.

The user has requested enhancement of the downloaded file.

 Advanced Topics of DFT Technologies in a General
Purposed CPU Chip
Yonglun Xu, Tao Lv, Wei Lu, Xiutao Ymg, Huawei Li, XiaoweiLi
( I . lnsiitufe of Computing Technology, CAS, Beijing 100080, P. R. China
2. Graduate School of the Chinese Academy of Sciences, Beijing 100039, P. K.China)
Email: (xyj, Ivtao, luwei, xiutaoyang lihuawei, Ixw)@ict.ac.cn

Abstract: Embedded memoiies could be difficult to exercise

Design-for-testability (DFT) is widely used in efficiently with functional or other types of testing. (c)
current integrated circuit design to enhance the Typical ATE testing may not adequately test memories.
controllability and obseivability of signals. The (d) Memories muld have high operating speeds [3]. So
technologies inseit extra logics into an original design, memory test is s vety impoitant issue of circuit designs.
running in test mode without any functional influence. Veiv luckily, an efficient method called memory BIST
How to make all the test logics work harmoniously and has been proved successful in menosy test and been
obtain high fault coverage wi!h low area and popular for years now. So some contents about memosy
performance overhead are the two main issues of DFT. BIST are firstly focused on in this paper.
Based on the design of a general-purposed CPU chip, With the increase of integration and operating
this paper introduces some advanced topics to conquer frequency, storage cells, like flip-flops and latches, are
the problems, including technologies of memoty build -in commonly used, which induced the emergence of
self-testing (BIST), inteinal scan design, logic BIST, internal scan design, here we just call it scan design,
IEEE Std. 1149.1 (JTAG)-compatible boundary scan which can be achieved by some commercial EDA tools,
design and the correlations among them. These such as DFTCompiler of Svnopsys and DFTAdvisor of
technologies offer a convenient and reliable DFT scheme Mentor Graphics Cotp. The main idea of scan design is
for digital circuit designs, especially for large-scale ones, to obtain controllability a d observability for memory
l k e a general-puiposed CPU chip. cells through scan chains in test mode. But for some
complicated designs, other special DFT technologies
Keywords : DFT,MBIST, Scm design, LBIST, BSD must be used in company with scan design to achieve
high fault coverage, such as test points insertion;
1. Introduction sequential test generation, RAM transpai-ent and maciu
Testhilit!. is a design attribute that measures how test [4,5] etc; which will be discussed later.
easy it is to ci-eate a program to coniprehensively test a Comparing u,ith memoly BIST, logic BIST is
manufactured design’s quality. The basic idea of test is, emerging to lower manufacturing test and system
setting specific values on the primary inputs i.esults in maintenance cost, which psovide the ability to test at
values on the primasy outputs which indicate whether or different levels as board level and system level. It
not the intemal circuitry works properly[ I]. Testable simplifies diagnostic testing and allow for at-speed
circuit17 is both conti-ollabla and observable. testing. It is such an attraztive technology that lots of
‘I’raditionally, design and test processes were kept articles work on it. Some issues about logic BIST are
separate, with test consdered only at the end of the also briefly discussed in this paper.
design flow But in contemporaty flows: test merges with Boundary scan design (BSD) is a standard DFT
design much earlier, creating what is called a technology [6,7]developed to supplement or replace the
design-for-test (DFT) pi-ocess flow [Z]. To ensure the “bed+f-nails” testing used with highly complex,
design with maximum testability, desiwers must employ multi-layer circuit boards, which has foimed IEEE
special DFT technologies at specific stages in the Std1149.1-1990 and IEEE Std1149.la-1993 (JTAG)
development process. For different logics, the DFT standards [SI. In out- project, BSD are not only used as
strategies can be veiy different, which we will detail interconnection test, hut also to suppot? board level
below. structural test, even functional test, acting a5 a master of
Most of today‘s designs benefit from embedded the ufhole chip.
memoiies, especially for SOCs (System on a Chip). Here
are some comnion side effects of using embedded 2. Memory BIST
memories in chips today: (a) Memory muld consume a
The first topic of DFT technologies we want to
large design portion and result in high defect rates. (b)
discuss is about memow test, because it can be done at
the design of register-transfer level and may have much
. This paper is suppotid by die National Nahrral Science Foundation more challenges. Memory BIST (Built-In Self-Test) has
of China (NSFC) under pant No.90207002 and in part by the National been used successfully for years to solve the test issues
High-Tech Project of China (863) under grant No.2001AA111100. of embedded memo ries. Memory BIST simplifies pattem
0-7803-7889-X/03/$I7.0002003 IEEE. 1179
fcneratioii. guai-antees high test quality by algorithmic
pattenis andieduces tiiuinpand'arq impact sigriificantly ,' 3 . :Scan,Design a?d,kTPGG;;; ':
' . ' : :

causedbp test logics. Mcinoi? RlST only adds a layer of

Scan design also divides designs into two operating
teat circuiti). around the memory, yhi,ch .becomes @e >,
modes. nomial : d n mode and test mode. This is done by
interface betwecn other logics and the RAM cores. ' '..
adding a test mode to the circuit such that when the
Figure I demonstrates the principle of memoly
circuit is in this mode, all flip-flops functionally form
BIST. 'The left side is the test logic used to generate test
one o.r more shift registers (scan chains). The inputs and
patterns; appk them on t h Mused RAM, and analyze
responses from it. The right part is a RAM under test outputs of these shift registers (also known as scan
registcrs; mux-DFF, clockcd- scan, and LSSD.) arc
wrapped in muz collars: The pattein generator is an FSM,
connected to priinaly inputs and primaly outputs. lhus,
in which some test algorithms. such as'MARCH, are
using the test mode, all flip-flops can be set t o any
realized to generate the test and control signals. The
response aiialyzer composed of a comparator or a XOR
desired states by shifting those logic states into the shift
compressor is used to compare output data with expected registers. Similarly, the states of flip-flops' i $ n ; b e
observed by shifting out the contents o f . the scan
values 'and decide .mheJher the RAM is OK. For the
registers.
application with a .large number of RAMS, multiple
Scan design methods' can be divided into three
RAMs can he tested under the snme,BIST controller to
save nrca and Ioiver the complexity of test logic. If the
strategies: full scan, partial scan and paitition scan. Full
RAM is v e n large. pipelines can be, also used to reduce scan is a scan,'design..niethodology that replaces all
memoll: elements in the design with their scannable
test time.
equivalents and then stitches them into scan chains. It's a
..I . . .
higbly' effectivc 'and predictable method with highly
automated process and' msured ,quality. Partial scan
replaces only a percentage of the storage elements, which
is. %e flexible between overhead (timing& area) and
fault coverage. Partition scan, which is often used on
vel). large and complex design; adds controllability and
obsrxvability to the design via hierarchical partition scan
chains. .. .,

Even if full scan method is used, a design can still

coniains a number of points that are difficult to control or
observe. We can increase the testability of the design by
Figure.l.Prinriple of hlemory BIST , adding special circuitry at certain locations called test
ents the basicinfoiniation of our F M s points, which can inject a logic value to the. point or
memo;? BIST. We use 7 controllei.s,to obsene the state of it at any time.
manipulate The 23 KAMs ofour CPU chip. The total area The most significant problem in scan design is the
is under 2% nf the whole chip. Tc>,pvoid the power test oC shadow logics, which'are the logics between the
consumption problems, w c test sequentially the RAMS, RAMS (or other macros) and'the first, layer of scan cells.
under the same conkdler., For DCache, icache and 'Bht There are t\Co methods to deal with the problem. One is
modules. we use, an efficient 17n MARCH,iigorithm [9] using sequential patteins to c o v x the. logi'cs. This
which can cover all the SAFs. TFs, SOFs, ,AFs, CFins, requires the R+Ms 'are .PIcontrollable.throughout test
and all linked CFids. d l '[Fs linked with CFids or CFins, procedures to prevent destroying the states of RAMS.
and some of CFins linked with CFids faults. The other method is to make the RAMs transparent in
As for the '.3wGif niodule, two special algoiithms test mode by connecting the inputs directly to the outputs
are d s o used: One is,port-interaction algorithm used to, and bypassing all the RAMs in test mode, this i s called
check for .shoi-Jed a d d m s lines on, ,different ports .and' RAM-transparent. But this method bould have too much
, . ,
ir&ig from one port ioithout any influence on any other overhead: I ,

r
read ports. The other is called unique address algorithm,
t? test the control signals and decoder circuitry. For the
multiple-port RAMS, "e also use 1ililc1.0,te:st to achieve
sonie fuiiclioilal test coverage, which mill be detailed
soon.

5661..31 78356

IJllh 1683 '' 4

toiiil. 592Rb 27 ' 7 ' 131203.97' ' *
. I

1180
 ~

Macro test is a utility that helps automate the testing generation and PRPG. Among them, PRPG made up of
of embedded logic and memories (macros) by LFSR (Linear Feedback Shift Register) is commonly
automatically translating usei--defined pattems for the used. MISR is also used.to calculate a test signature from
macros into scan pattems [IO]. Because it enables us to the circuit under test. Phase shifter and compactor are
apply our macro test' vectors in the embedded usually added to improve the characters of PRPG and
environment, macro test improves overall IC test quality MISR. Here, the scan chains of the full scanned target
without any impact on area and perfomiance of DUT. circuits are called STUMPS channels.
r--------------
This is illustrated conceptually in Figure 2. With the help
of macro test, scan design test coverage. of our chip
reaches above 9W.
MSB LSB !
Because our chip will work at very high speed, not
only s t u c k 4 and IDDQ faults are tested, hut also toggle
and transition faults. Test pattems aiming at these
high-quality faults can be imp1eme;ted on ATE as well
as SA faults. To reach high fault coverage and low design
overhead, full scan design is implemented with standard
mux-DFF scan cells in the DFT of oui- chip. As a whole,
38 AND-type test points ai-e inserted to make all the
RAMS controllable f~-ointhe primary inputs, so we can
use rain-sequential to obtain high fault coverage. Macro
test technology is also used to vetify to the function of
some modules, such as 3w6r and Dtlb modules.
F i m r e 4. Multi-phase test point activation
4. Logic BIST If an X propagates to an observe point, the single
good machine signature condition will get corrupted.
Classical testing uses exteinal test pattems as
Un-initialized RAMS and non-scan flip-flops are the
stimulus, and applies them to the device via a tester. The
main source of X. We can initialize the RAMS and make
tester examines the device's response aid compares it
them read-only during test or isolate the RAMS using
with the known good response stored as part of the test
RAM-transparent method mentioned above. We should
pattern data. However, logic BIST achieves these works
similarly initialize all the memory flip-flops to prevent
within 'the design and provides a way to reduce tester
un-initialized data from reaching the MISR. We should
time without sacrificing test quality. Figure 3
also deal with transparent-latch, tri-state buses, TIE-X
demonstrates the principle of logic B E T mainly
and other X sources.
composed of a BIST controller; PRPG pseudo Random
For logic BISTed circuits, fault coverage often can't
Patten? Generator), MISR (Multiple Input Signature
reach very high because of aliasing [ II] and existence of
Register) and STUMPS channels (Self-Test Usiiig
too many hard to excite faults. Lots of works have been
MISRParallel SRSG Shift Register Sequence
proposed in this. Test point insertion is an efficient and
Generator). Logic BIST controller is the headquarters of
low-overhead method to overcome the random pattem
all the BIST logics, dominating interaction of internal i
resistance W R ) problem As figure 4 shows, y e C M use
and exteinal sienals.
a phase decoder to enable different test points activated
r------------ 1 during each phase [I21 of pattem counter. Probabilistic
I fault simulations are also used to select the optimal set of
control and observation points that contribute to the
I maximum improvement of fault coverage using the
I fewest test points.
I 5. Boundary Scan Design
I
Boundary scan is an IEEE standard protocol that
I not only benefits the board level testing of ICs and PCU
I interconnects, but also offers a standard System Test Port
I and Bus making it possible to integrate components from
different vendors.
1 Fundamentally, boundary scan design places
I interconnected boundary scan cells around a device's
Figure.3 Principle of Logic BIST core logic, fanning a boundary scan register. The test
data can be serially loaded onto evely pin through one
There ai-e many approaches to generate logic BIST scan input and unloaded through a single scan output.
pattems incluaing ROM, LFSR, binary counters, cellular The test operation is controlled by a standard Test Access
automatioii etc; which often fall into three categories: Port (TAP) and four or five pin interface - TCK [test
exhaustive pattem generation, pseudo -exhaustive pattem clock), TDI (test data in), TDO (test data out), TMS (test

1181
 mode select) and TRST (an optional test reset). All instruction register controls the boundaly scan circuitiy
bouiidai). scan opei-ations can be controlled through just by connecting a specific test data register between the
this iiitei-face. Figure 5 gives the extemal interconnection TDI and TDO pins using a predefined set of instructions.
between the DFTed core and boundary scan logics. All (3)Test data registers include BIST and internal scan
the pins except power aiid ground of the core are paths connecting directly to the core. (4)The instruction
connected into the boundary scan chain and controlled decoder translates the instruction to control the data
b:\: TAP controller. Figure 5 also gives a blueprint of registers. (5)The Mu,: module controls the data flows‘
BSDed logic BIST and scan design, which can be freely
controlled by TAF on hoard aiid v s t e m level.
directions.
.------------- -___ I

Test Data Reg

Figure 6. Boundary Scan architecture

Figure.5 B o n d test using boundnry scan 6. Conclusions

Figure 6 presents a module scheme of boundary
In this paper, some advanced topics of DFT
scan architecture, which is mainly composed of five parts.
technologies are discussed including memory BIST, scan
(lyi‘he TAP controller is a finite state machine that
design, logic BIST and BSD. The ideas are implemented
controls thc opcration of thc instruction and test data
on a general-purposed CPU chip and have been proven
registers. The TAP controller’s state depends on thevalue
of TMS line at each clock pulse (TCK). (2)The

Reference:

[ I ] Michael I>. Buslmell, Vishwani D. Agrawal. Essentials (of Electronic Testing for Digital, Memoiy and
Mi~ed-SignalVLSI Circuits, Kluwer Academic Publishers, 2000.
121 T.W. Williams and K.Parker, ”Design for Testability - A Survey”, IEEE Trans. on Computers, vol. C-31, no.],
Jan 1982; P ? - l i
[3] Mentor Graphics Corp. “Memoiy BIST Training Workbook,“ Software Version V8.2002-2, June 2002.
141 F. Beenker, K. Eerdewijk, et al. “Macro Testing: Unifying IIC and Board Test. IEEE Design & Test of
Computers“, Vol. 3, No. 4, December 1986, P26-32.
[j]F. Beenket-, B. Bennetts and L. Tijssen, “Testability Concepts for Digital ICs-the Macro Test Approach”, vol; 3
of Frontiers in Electronic Testing. Kluwer Academic F’ublishers,Boston, 1995.
[6] Michael L. Bushiell, Vishwani D. Agrawal. “Essentials of Electronic Testing for Digital, Memory and
Mixed-Signal VLSI Circuits:” Kluwer Academic Publishers, 2000.
[7] C.M. Maunder and R.E.Tulloss, The Test Access Port and Boundary Scan Architecture. Los Alamitos, Califomia:
IEEE Computer Society Press. Sept. 1990.
[8] IEEE Staiidards Board, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1994
191 D. S.Suk and S. M. Reddv, “A March Test for Functional Faults in Semiconductor RandomAccess Memories,”
IEEE trans. On Computers, Vol. C-30,No.12, Dec.1981, P982-985.
[IO] Mentor Graphics Coip. ‘‘ Scan and ATPG Process Guide”, Software Version V8.2002-2, June 2002.
[ I I ] T.W.Willians, W.Daehn, M.Gruetzner, and C.W. Starke, “Bounds and Analysis of Aliasing Errors in
Lineai=FeedhackShift-Registers.“ IEEE Trans. On Computer-Aided Design, Vol. CAD7, no. 1, Jan, 1988, P75-83.
[I?] J. Ra.iski and J. Tyzer, “Arithmetic Built-In Self-Test for Embedded Systems.” Upper Saddle River, New Jerse:\::
Prentice-Hall, 1998.

1182

View publication stats