NCV6357

Step Down Converter, AOT,

Configurable 5.0 A
The NCV6357 is a synchronous AOT (Adaptive On−time) buck
converter optimized to supply the different sub systems of automotive
applications post regulation system up to 5 V input. The device is able
to deliver up to 5.0 A, with programmable output voltage from 0.6 V www.onsemi.com
to 3.3 V. Operation at up to 2.4 MHz switching frequency allows the
MARKING
use of small components. Synchronous rectification and automatic
DIAGRAM
PFM Pseudo−PWM (PPWM) transitions improve overall solution
efficiency. The NCV6357 is in low profile 3.0 × 4.0 mm DFN−14
1
package. 6357
WDFNW14 4x3, 0.5P XX
Features CASE 511CM AYWW
• Input Voltage Range from 2.5 V to 5.5 V: Battery, 3.3 V and 5.0 V G
Rail Powered Applications
• Power Capability: 3.0 A TA = 105°C − 5.0 A TA = 85°C XX = A: 1.80 V /1.10 V
= B: 0.90 V / 1.00 V
• Programmable Output Voltage: 0.6 V to 3.3 V in 12.5 mV Steps
= C: 1.80 V /1.10 V
• Up to 2.4 MHz Switching Frequency with On Chip Oscillator = D: 1.25 V / 1.25 V
• Uses 330 nH Inductor and at Least 22 mF Capacitors for Optimized = F: 1.00 V / 1.10 V
A = Assembly Location
Footprint and Solution Thickness Y = Year
• PFM/PPWM Operation for Optimum Efficiency WW = Work Week
• Low 60 mA Quiescent Current G = Pb−Free Package

• I2C Control Interface with Interrupt and Dynamic Voltage Scaling (Note: Microdot may be in either location)
Support
• Enable / VSEL Pins, Power Good / Interrupt Signaling PIN CONNECTIONS
• Thermal Protections and Temperature Management (Top View)
14− Pin 0.50 mm pitch
• Transient Load Helper: Share the Same Rail with another Rail DFN
• 3.0 × 4.0 mm / 0.5 mm Pitch DFN 14 Package
• AEC−Q100 Qualified and PPAP Capable
Typical Applications
• Snap Dragon
• Automotive POL
• Instrumentation, Clusters
• Infotainment
• ADAS System (Vision, Radar)

Supply Input NCV6357

AVIN
4.7 mF AGND PVIN Supply Input
Core

Thermal 10 mF
Protection
DCDC
Enable Control EN 5A
Input SW
Operating
Mode Modular 330 nH
Voltage VSEL Control Driver
Selection
2 × 22 mF

PG Output PGND
Power Good
Monitoring

FB

Processor I2C SDA

GND
I2C
DCDC
2.4 MHz Sense
Processor
Core
ORDERING INFORMATION
Controller
Control Interface GND See detailed ordering and shipping information on page 32 of
SCL
this data sheet.

Figure 1. Typical Application Circuit

© Semiconductor Components Industries, LLC, 2018 1 Publication Order Number:

January, 2019 − Rev. 3 NCV6357/D
 NCV6357

PVIN POWER INPUT

PVIN

SUPPLY INPUT AVIN

Core
ANALOG GROUND AGND
SW
5.0 A
Thermal DC−DC SW SWITCH NODE
Protection
SW

Output Voltage
Monitoring

ENABLE CONTROL INPUT EN Up to 2.4 MHz

Operating
DC−DC converter
VOLTAGE SELECTION VS EL Mode Control
Controller
PGND POWER GROUND
PGND
PG Logic Control
PROCESSOR I2C VOUT
CONTROL INTERFACE SCL Power Good Sense FEEDBACK

SDA I2C

Figure 2. Simplified Block Diagram

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 NCV6357

Figure 3. Pin Out (Top View)

PIN FUNCTION DESCRIPTION

Pin Name Type Description
REFERENCE
4 AVIN Analog Input Analog Supply. This pin is the device analog and digital supply. Could be connected
directly to the VIN plane with a dedicated 4.7 mF ceramic capacitor. Must be equal to
PVIN
15 AGND Analog Analog Ground. Analog and digital modules ground. Must be connected to the system
Ground ground

CONTROL AND SERIAL INTERFACE

14 EN Digital Input Enable Control. Active high will enable the part. There is an internal pull down resistor
on this pin

13 VSEL Digital Input Output voltage / Mode Selection. The level determines which of two programmable
configurations to utilize (operating mode / output voltage). There is an internal pull down
resistor on this pin; could be left open if not used
3 PG Digital Power Good Indicator open drain output. Must be connected to the ground plane if
Output not used

1 SCL Digital Input I2C interface Clock line. There is an internal pull down resistor on this pin; could be left
open if not used

12 SDA Digital I2C interface Bi−directional Data line. There is an internal pull down resistor on this pin;
Input/Output could be left open if not used

DC TO DC CONVERTER
8, 9 PVIN Power Input Switch Supply. These pins must be decoupled to ground by at least a 10 mF ceramic
capacitor. It should be placed as close as possible to these pins. All pins must be used
with short heavy connections. Must be equal to AVIN
5, 6, 7 SW Power Switch Node. These pins supply drive power to the inductor. Typical application uses
Output 0.33 mH inductor; refer to application section for more information.
All pins must be used with short heavy connections
10, 11 PGND Power Switch Ground. This pin is the power ground and carries the high switching current.
Ground High quality ground must be provided to prevent noise spikes. To avoid high−density
current flow in a limited PCB track, a local ground plane that connects all PGND pins
together is recommended. Analog and power grounds should only be connected
together in one location with a trace
2 VOUT Analog Input Feedback Voltage input. Must be connected to the output capacitor positive terminal
with a trace, not to a plane. This is the positive input to the error amplifier

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 NCV6357

MAXIMUM RATINGS
Rating Symbol Value Unit
Analog and power pins (Note 1):
AVIN, PVIN, SW, PG, VOUT, DC non switching VA − 0.3 to + 6.0 V
PVIN−PGND pins, transient 3 ns – 2.4 MHz −0.3 to +7.5
I2C pins: SDA, SCL VI2C − 0.3 to + 6.0 V
Digital pins : EN, VSEL
Input Voltage VDG −0.3 to VA +0.3 ≤ 6.0 V
Input Current IDG 10 mA
Human Body Model (HBM) ESD Rating (Note 2) ESD HBM 2500 V
Charged Device Model (CDM) ESD Rating (Note 2) ESD CDM 2000 V
Latch Up Current: (Note 3) ILU
Digital Pins 100 mA
All Other Pins 100
Storage Temperature Range TSTG − 65 to + 150 °C
Maximum Junction Temperature TJMAX −40 to +150 °C
Moisture Sensitivity (Note 4) MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) ±2.5 kV per JEDEC standard: JESD22*A114.
Charged Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 Class IV
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.

OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
AVIN, PVIN Power Supply AVIN = PVIN 2.5 5.5 V
TJ Junction Temperature Range (Note 6) − 40 25 +125 °C
RqJA Thermal Resistance Junction to Ambient (Note 7) DFN−14 on Demo−board − 30 − °C/W
PD Power Dissipation Rating (Note 8) TA ≤ 105°C, − 666 − mW
RqJA = 30°C/W
TA ≤ 85°C − 1333 − mW
RqJA = 30°C/W
TA = 65°C − 2000 − mW
RqJA = 30°C/W
L Inductor for DC to DC converter (Note 5) 0.15 0.33 0.47 mH
Co Output Capacitor for DC to DC Converter (Note 5) 15 − 200 mF
Cin Input Capacitor for DC to DC Converter (Note 5) Per 1.0 A of IOUT 6.0 10.0 − mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a NCV6357EVB board. It is a multilayer board with
1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
8. The maximum power dissipation (PD) is dependent on input voltage, maximum output current, pcb stack up and layout, and external
components selected.

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 NCV6357

ELECTRICAL CHARACTERISTICS (Note 9)

Min and Max Limits apply for TJ = −40°C to +125°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Typical values are referenced to TA = + 25°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
SUPPLY CURRENT: PINS AVIN – PVINx
IQ−PPWM Operating quiescent current PPWM DCDC active in Forced − 22 25 mA
PPWM no load

IQ PFM Operating quiescent current PFM DCDC active in Auto mode − 60 90 mA

no load – minimal switching

ISLEEP Product sleep mode current Product in sleep mode − 5 10 mA

VIN = 5.5 V, TJ up to 85°C
IOFF Product in off mode EN, VSEL and Sleep_Mode − 0.8 3 mA
low, No I2C pull up
VIN = 5.5 V, TJ up to 85°C
DC TO DC CONVERTER
PVIN Input Voltage Range 2.5 − 5.5 V
IOUT Load Current Range (Note 11, 12) A
Ipeak[1..0] = 00 0 − 3.5
Ipeak[1..0] = 01 0 − 4.0
Ipeak[1..0] = 10 0 − 4.5
Ipeak[1..0] = 11 0 − 5.0
DVOUT Output Voltage DC Error Forced PPWM mode, No −1.5 − 1.5 %
load

Forced PPWM mode, −2 − 2

IOUT up to IOUTMAX (Note 11)
Auto mode, −3 − 2
IOUT up to IOUTMAX (Note 11)
FSW Switching Frequency 2.16 2.4 2.64 MHz
RONHS P−Channel MOSFET On Resistance From PVIN to SW − 39 60 mΩ
VIN = 5.0 V
RONLS N−Channel MOSFET On Resistance From SW to PGND − 32 45 mΩ
VIN = 5.0 V
IPK Peak Inductor Current Open loop − Ipeak[1..0] = 00 4.6 5.2 5.8 A
Open loop − Ipeak[1..0] = 01 5.2 5.8 6.4
Open loop − Ipeak[1..0] = 10 5.6 6.2 6.8
Open loop − Ipeak[1..0] = 11 6.2 6.8 7.4

IPKN Negative Current limit − 1.4 − A

DCLOAD Load Regulation IOUT from 0 A to IOUTMAX − 5 − mV
Forced PPWM mode
DCLINE Line Regulation 2.5 V ≤ VIN ≤ 5.5 V − 6 − mV
Forced PPWM mode
ACLOAD Transient Load Response tr = tf = 100 ns − ±20 − mV
Load step 1.5 A
ACLINE Transient Line Response tr = tf = 10 ms − ±20 − mV
Line step 3.0 V / 3.6 V
D Maximum Duty Cycle − 100 − %
tSTART Turn on time Time from EN transitions − 100 130 ms
from Low to High to 90% of
Output Voltage
(DVS[1..0] = 00b),
VOUT = 1.10 V
RDISDCDC DCDC Active Output Discharge VOUT = 1.10 V − 12 25 Ω

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 NCV6357

ELECTRICAL CHARACTERISTICS (Note 9)

Min and Max Limits apply for TJ = −40°C to +125°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Typical values are referenced to TA = + 25°C, AVIN = PVIN = 3.3 V and default configuration, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
EN, VSEL
VIH High input voltage 1.05 − − V
VIL Low input voltage − − 0.4 V
TFTR Digital input X Filter EN, VSEL rising and falling 0.5 − 4.5 ms
DBN_Time = 01 (Note 11)
IPD Digital input X Pull−Down For EN and VSEL pins − 0.05 1.00 mA
(input bias current)
PG (OPTIONAL)
VPGL Power Good Threshold Falling edge as a percentage 86 90 94 %
of nominal output voltage

VPGHYS Power Good Hysteresis 0 3 5 %

TRT Power Good Reaction Time for DCDC Falling (Note 11) − 1.0 − ms
Rising (Note 11) 3.5 − 14
VPGL Power Good low output voltage IPG = 5 mA − − 0.2 V
PGLK Power Good leakage current 3.3V at PG pin when power − − 100 nA
good valid

VPGH Power Good high output voltage Open drain − − 5.5 V

I2C
VI2CINT High level at SCL/SCA line 1.7 − 4.5 V
VI2CIL SCL, SDA low input voltage SCL, SDA pin − − 0.4 V
VI2CIH SCL high input voltage SCL pin (Note 10, 11) 1.6 − − V
SDA high input voltage SDA pin (Note 10, 11) 1.2 − −
VI2COL SDA low output voltage ISINK = 3 mA − − 0.4 V
FSCL I2C clock frequency (Note 11) − − 3.4 MHz
TOTAL DEVICE
VUVLO Under Voltage Lockout VIN falling − − 2.5 V
VUVLOH Under Voltage Lockout Hysteresis VIN rising 60 − 200 mV
TSD Thermal Shut Down Protection − 150 − °C
TWARNING Warning Rising Edge − 135 − °C
TPWTH Pre–Warning Threshold I2C default value − 105 − °C
TSDH Thermal Shut Down Hysteresis − 30 − °C
TWARNINGH Thermal warning Hysteresis − 15 − °C
TPWTH H Thermal pre−warning Hysteresis − 6 − °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Refer to the Application Information section of this data sheet for more details.
10. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to
the VDD voltage to which the pull−up resistors RP are connected.
11. Guaranteed by design and characterized.
12. Junction temperature must be maintained below 125°C. Output load current capability depends on the application thermal capability.

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 NCV6357

TYPICAL OPERATING CHARACTERISTICS AVIN = PVIN = 3.3 V, TJ = +25°C

DCDC = 1.80 V, IPEAK = 6.8 A (Unless otherwise noted). L = 0.33 mH DFE252012F – COUT = 2 x 22 mF 0603, CIN = 4.7 mF 0603.

Figure 4. Efficiency vs ILOAD and VIN Figure 5. Efficiency vs ILOAD and Temperature
VOUT = 3.3 V, SPM5030 Inductor VOUT = 3.3 V, VIN = 5.0 V, SPM5030 Inductor

Figure 6. Efficiency vs ILOAD and VIN Figure 7. Efficiency vs ILOAD and Temperature
VOUT = 1.8 V, SPM5030 Inductor VOUT = 1.8 V, SPM5030 Inductor

Figure 8. Efficiency vs ILOAD and VIN Figure 9. Efficiency vs ILOAD and Temperature
VOUT = 0.60 V, SPM5030 Inductor VOUT = 0.60 V, SPM5030 Inductor

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 NCV6357

Figure 10. Efficiency vs ILOAD and VIN Figure 13. Efficiency vs ILOAD and Temperature
VOUT = 1.80 V VOUT = 1.80 V

Figure 11. Efficiency vs ILOAD and VIN Figure 12. Efficiency vs ILOAD and VIN
VOUT = 0.60 V VOUT = 1.10 V

Figure 15. Efficiency vs ILOAD and VIN Figure 14. Efficiency vs ILOAD and VIN
VOUT = 1.25 V VOUT = 3.30 V

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 NCV6357

Figure 17. VOUT Accuracy vs ILOAD and VIN Figure 18. VOUT Accuracy vs VIN and Temperature
VOUT = 1.80 V VOUT = 1.80 V

Figure 20. VOUT Accuracy vs ILOAD and VIN Figure 21. VOUT Accuracy vs ILOAD and VIN
VOUT = 0.600 V VOUT = 1.10 V

Figure 19. VOUT Accuracy vs ILOAD and VIN Figure 16. VOUT Accuracy vs ILOAD and VIN
VOUT = 1.25 V VOUT = 3.3 V

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 NCV6357

Figure 22. HSS RON vs VIN and Temperature Figure 27. LSS RON vs VIN and Temperature

Figure 23. IOFF vs VIN and Temperature Figure 24. ISLEEP vs VIN and Temperature

Figure 25. IQ PFM vs VIN and Temperature Figure 26. IQ PPWM vs VIN and Temperature
VOUT = 1.25 V VOUT = 1.25 V

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 NCV6357

Figure 28. Switchover Point VOUT = 1.15 V Figure 29. Switchover Point VOUT = 1.4 V

Figure 30. Switching Frequency vs ILOAD and VIN Figure 31. Switching Frequency vs ILOAD and
VOUT = 1.10 V Temperature VOUT = 1.10 V

Figure 32. Ripple Figure 33. Normal Power Up, VOUT = 1.15 V
DVS[1..0] = 00

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 NCV6357

Figure 34. Transient load 0.05 to 1.5 A Figure 35. Transient load 0.05 to 1.5 A
Transient line 3.0 – 3.6 V Auto mode Transient line 3.6 – 3.0 V Auto mode

Figure 36. Transient load 0.05 to 1.5 A Figure 37. Transient load 0.05 to 1.5 A
Transient line 3.0 – 3.6 V Forced PPW Transient line 3.6 – 3.0 V Forced PPWM

Figure 38. Transient load 1.0 to 2.5 A Figure 39. Transient load 2.0 to 3.5 A

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 NCV6357

DETAILED OPERATING DESCRIPTION

Detailed Descriptions Output Stage

The NCV6357 is voltage mode stand−alone DC to DC NCV6357 is a 3.5 A to 5.0 A output current capable DC
converter optimized to supply different sub systems of to DC converter with both high side and low side
automotive applications post regulation system up to 5 V (synchronous) switches integrated.
input. It can deliver up to 5 A at an I2C selectable voltage
Inductor Peak Current Limitation / Short Protection
ranging from 0.6 V to 3.3 V. The switching frequency up to
2.4 MHz allows the use of small output filter components. During normal operation, peak current limitation
Power Good indicator and Interrupt management are monitors and limits the inductor current by checking the
available. Operating modes, configuration, and output current in the P−MOSFET switch. When this current
power can be easily selected either by using digital I/O pins exceeds the Ipeak threshold, the P−MOSFET is immediately
or by programming a set of registers using an I2C compatible opened.
interface capable of operation up to 3.4 MHz. To protect again excessive load or short circuit, the
Default I2C settings are factory programmable. number of consecutive Ipeak is counted. When the counter
reaches 16, the DCDC is powered down during about 2 ms
DC to DC Converter Operation and the ISHORT interrupt is flagged. It will re−start
The converter integrates both high side and low side following the REARM bit in the LIMCONF register:
(synchronous) switches. Neither external transistors nor • If REARM = 0, then NCV6357 does not re−start
diodes are required for NCV6357 operation. Feedback and automatically, an EN pin toggle is required
compensation network are also fully integrated. • If REARM = 1, NCV6357 re−starts automatically after
It uses the AOT (Adaptive On−Time) control scheme and the 2 ms with register values set prior the fault
can operate in two different modes: PFM and PPWM condition
(Pseudo−PWM). The transition between modes can occur
automatically or the switcher can be placed in forced PPWM This current limitation is particularly useful to protect the
mode by I2C programming (PPWMVSEL0 / PPWMVSEL1 inductor. The peak current can be set by writing
bits of COMMAND register). IPEAK[1..0] bits in the LIMCONF register.
PPWM (Pseudo Pulse Width Modulation) Operating
Mode Table 1. IPEAK VALUES
In medium and high load conditions, NCV6357 operates IPEAK[1..0] Inductor Peak Current (A)
in PPWM mode to regulate the desired output voltage. In
00 5.2 – for 3.5 output current
this mode, the inductor current is in CCM (Continuous
Conduction Mode) and the AOT guaranties a pseudo−fixed 01 5.8 – for 4.0 output current
frequency with 10% accuracy. The internal N−MOSFET 10 6.2 – for 4.5 output current
switch operates as synchronous rectifier and is driven 11 6.8 – for 5.0 output current
complementary to the P−MOSFET switch.
PFM (Pulse Frequency Modulation) Operating Mode To protect the low side switch, the negative current
In order to save power and improve efficiency at low protection limits potential excessive current from output.
loads, the NCV6357 operates in PFM mode as the inductor
Output Voltage
current drops into DCM (Discontinuous Conduction Mode).
The output voltage is set internally by an integrated
The upper FET on−time is kept constant and the switching
resistor bridge and no extra components are needed to set the
frequency becomes proportional to the loading current. As
output voltage. Writing in the VoutVSEL0[7..0] bits of the
it does in PPWM mode, the internal N−MOSFET operates
PROGVSEL0 register or VoutVSEL1[7..0] bits of the
as a synchronous rectifier after each P−MOSFET on−pulse
PROGVSEL1 register will change the output voltage. The
until there is no longer current in the coil.
output voltage level can be programmed by 12.5 mV steps
When the load increases and the current in the inductor
between 0.6 V to 3.3 V. The VSEL pin and VSELGT bit will
become continuous again, the controller automatically turns
determine which register between PROGVSEL0 and
back to PPWM mode.
PROGVSEL1 will set the output voltage.
Forced PPWM • If VSELGT = 1 AND VSEL = 0 ³ Output voltage is
The NCV6357 can be programmed to only use PPWM set by VoutVSEL0[7..0] bits (PROGVSEL0 register)
and the transition to PFM can be disabled if so desired,
• Else ³ Output voltage is set by VoutVSEL1[7..0] bits
thanks to the PPWMVSEL0 or PPWMVSEL1 I2C bits
(PROGVSEL1 register)
(COMMAND register).

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 NCV6357

Under Voltage Lock Out (UVLO) discharge path is enabled and is activated during the first
NCV6357 core does not operate for voltages below the 100 ms after battery insertion.
Under Voltage Lock Out (UVLO) level. Below the UVLO
threshold, all internal circuitry (both analog and digital) is Enabling
held in reset. NCV6357 operation is guaranteed down to The EN pin controls NCV6357 start up. EN pin Low to
UVLO as the battery voltage is dropping off. To avoid erratic High transition starts the power up sequencer. If EN is low,
on / off behavior, a maximum 200 mV hysteresis is the DC to DC converter is turned off and device enters:
implemented. Restart is guaranteed at 2.7 V when the VBAT • Sleep Mode if Sleep_Mode I2C bit is high or VSEL is
voltage is recovering or rising. high or I2C pull up present
• Off Mode if Sleep_Mode I2C bit and VSEL are low and
Thermal Management
no I2C pull up
Thermal Shut Down (TSD)
Battery monitoring for UVLO and Overvoltage When EN pin is set to a high level, the DC to DC converter
Protectione thermal capability of the NCV6357 can be can be enabled / disabled by writing the ENVSEL0 or
exceeded due to the step down converter output stage power ENVSEL1 bit of the COMMAND registers:
level.. A thermal protection circuitry with associated • Enx I2C bit is high, the DC to DC converter is
interrupt is therefore implemented to prevent the IC from activated.
damage. This protection circuitry is only activated when the • Enx I2C is low, the DC to DC converter is turned off
core is in active mode (output voltage is turned on). During and the device enters in Sleep Mode.
thermal shut down, output voltage is turned off.
During thermal shut down, the output voltage is turned A built in pull down resistor disables the device when this
off. pin is left unconnected or not driven. EN pin activity does
When NCV6357 returns from thermal shutdown, it can not generate any digital reset.
re−start in 2 different configurations depending on the Power Up Sequence (PUS)
REARM bit in the LIMCONF register (refer to the register In order to power up the circuit, the input voltage AVIN
description section): has to rise above the VUVLO threshold. This triggers the
• If REARM = 0 then NCV6357 does not re−start after internal core circuitry power up which is the “Wake Up
TSD. To restart, an EN pin toggle is required Time” (including “Bias Time”).
• If REARM = 1, NCV6357 re−starts with register values This delay is internal and cannot be bypassed. EN pin
set prior to thermal shutdown transition within this delay corresponds to the “Initial power
up sequence” (IPUS):
The thermal shut down threshold is set at 150°C (typical) AVIN
and a 30°C hysteresis is implemented in order to avoid
erratic on / off behavior. After a typical 150°C thermal shut UVLO
POR
down, NCV6357 will resume to normal operation when the

ÉÉÉÉ
EN
die temperature cools to 120°C.
Thermal Warnings
In addition to the TSD, the die temperature monitoring
circuitry includes a thermal warning and thermal
VOUT ÉÉÉÉ
∼ 80 ms
DELAY[2..0]
32 ms

pre−warning sensor and interrupts. These sensors can Wake up Init DVS ramp
inform the processor that NCV6357 is close to its thermal Time Time Time

shutdown and preventive measures to cool down die Figure 40. Initial Power Up Sequence
temperature can be taken by software.
The Warning threshold is set by hardware to 135°C In addition a user programmable delay will also take place
typical. The Pre−Warning threshold is set by default to between the Wake Up Time and the Init time: The
105°C but it can be changed by setting the TPWTH[1..0] bits DELAY[2..0] bits of the TIME register will set this user
in the LIMCONF register. programmable delay with a 2 ms resolution. With default
delay of 0 ms, the NCV6357 IPUS takes roughly 100 ms, and
Active Output Discharge the DC to DC converter output voltage will be ready within
To make sure that no residual voltage remains in the power 150 ms.
supply rail when disabled, an active discharge path can The power up output voltage is defined by the VSEL state.
ground the NCV6357 output voltage. For maximum NOTE: During the Wake Up time, the I2C interface is
flexibility, this feature can be easily disabled or enabled with not active. Any I2C request to the IC during this
the DISCHG bit in the PGOOD register. By default the time period will result in a NACK reply.

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 NCV6357

Normal, Quick and Fast Power Up Sequence DC to DC Converter Shut Down

The previous description applies only when the EN When shutting down the device, no shut down sequence
transitions during the internal core circuitry power up (Wake is required. The output voltage is disabled and, depending on
up and calibration time). Otherwise 3 different cases are the DISCHG bit state of the PGOOD register, the output may
possible: be discharged.
• Enabling the part by setting the EN pin from Off Mode DC to DC converter shutdown is initiated by either
will result in “Normal power up sequence” (NPUS, grounding the EN pin (Hardware Shutdown) or, depending
with DELAY;[2..0]) on the VSEL internal signal level, by clearing the ENVSEL0
or ENVSEL1 bits (Software shutdown) in the PROGVSEL0
• Enabling the part by setting the EN pin from Sleep or PROGVSEL1 registers.
Mode will result in “Quick power up sequence” In hardware shutdown (EN = 0), the internal core is still
(QPUS, with DELAY;[2..0]) active and I2C accessible.
• Enabling the DC to DC converter, whereas EN is The internal core of the NCV6357 shuts down when AVIN
already high, either by setting the ENVSEL0 or falls below UVLO.
ENVSEL1 bits or by VSEL pin transition will results in
Dynamic Voltage Scaling (DVS)
“Fast power up sequence” (FPUS, without
DELAY[2..0]) The NCV6357 supports dynamic voltage scaling (DVS)
allowing the output voltage to be reprogrammed via I2C
AVIN
commands and provides the different voltages required by
the processor. The change between set points is managed in
UVLO
POR
a smooth fashion without disturbing the operation of the
EN O
processor.
F When programming a higher voltage, the output raises
F
with controlled dV/dt defined by DVS[1..0] bits in the TIME
register. When programming a lower voltage the output
60 ms

M DELAY[2..0]
32 ms
O voltage will decrease accordingly. The DVS step is fixed and
D
E the speed is programmable.
TFTR Bias
Time
Init DVS ramp
Time Time
The DVS sequence is automatically initiated by changing
the output voltage settings. There are two ways to change
Figure 41. Normal Power Up Sequence these settings:
AVIN
• Directly change the active setting register value
UVLO
POR
(VoutVSEL0[7..0] of the PROGVSEL0 register or
S
EN L
VoutVSEL1[7..0] of the PROGVSEL1 register) via an
E I2C command
E
P • Change the VSEL internal signal level by toggling the
VSEL pin
10 ms

M DELAY[2..0]
32 ms
O
D
E The second method eliminates the I2C latency and is
TFTR Bias
Time
Init DVS ramp
Time Time
therefore faster.
The DVS transition mode can be changed with the
Figure 42. Quick Power Up Sequence
AVIN
DVSMODE bit in the COMMAND register:
• In forced PPWM mode when accurate output voltage
UVLO
POR control is needed. Rise and fall time are controlled with
S
VSEL L the DVS[1..0] bits
E
E
P Internal V2 Output
VOUT M Reference Voltage
32 ms
O DV
D
E
Dt
T Init DVS ramp
Time Time V1

Figure 43. Fast Power Up Sequence

Figure 44. DVS in Forced PPWM Mode Diagram
Output
In addition the delay set in DELAY[2..0] bits in TIME Internal V2
Voltage
register will apply only for the EN pins turn ON sequence Reference
DV
(NPUS and QPUS).
The power up output voltage is defined by VSEL state. Dt
V1

Figure 45. DVS in Auto Mode Diagram

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 NCV6357

Power Good Pin Digital IO Settings

To indicate the output voltage level is established, a power VSEL pin
good signal is available on PG pin. The power good signal By changing VSEL pin levels, the user has a latency free
is low when the DC to DC converter is off. Once the output way to change NCV6357 configuration: operating mode
voltage reaches 93% of the expected output level, the power (Auto or PWM forced), the output voltage as well as enable.
good logic signal becomes high and the open drain output
becomes high impedance. Table 2. VSEL PIN PARAMETERS
During operation, when the output drops below 90% of
Parameter VSEL REGISTER REGISTER
the programmed level, the power good logic signal goes low, Pin Can Set VSEL = LOW VSEL = HIGH
indicating a power failure. When the voltage rises again to
above 93%, the power good signal goes high again. ENABLE ENVSEL0 ENVSEL1
During a DVS sequence, the Power Good signal is set low COMMAND[3] COMMAND[2]
during the transition and goes back to high once the VOUT VoutVSEL0[7..0] VoutVSEL1[7..0]
transition is completed.
OPERATING PWMVSEL0 PWMVSEL1
The Power Good signal during normal operation can be MODE (Auto / COMMAND[7] COMMAND[6]
disabled by clearing the PGDCDC bit in the PGOOD PPWM Forced)
register.
The Power Good operation during DVS can be activated VSEL pin action can be masked by writing 0 to the
with PGDVS bit of the PGOOD register. VSELGT bit in the COMMAND register. In that case I2C bit
corresponding to VSEL high will be taken into account.
DCDC_EN EN pin
93 % The EN pin can be gated by writing the ENVSEL0 or
32 ms 90 % ENVSEL1 bits of the COMMAND register, depending on
DCDC
3.5−
1.0 ms
3.5− which register is activated by the VSEL internal signal.
14 ms 14 ms
Interrupt (Optional)
PG The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when
Figure 46. Power Good signal when PGDCDC = 1
a system status change is detected (dual edge monitoring).
Internal Table 3. INTERUPT SOURCES
DVS ramp
Interrupt Name Description
TSD Thermal Shut Down
V1
DVS DVS TWARN Thermal Warning
up down
TPREW Thermal Pre−Warning
PG UVLO Under Voltage Lock Out
IDCDC DC to DC converter Current
Over / below limit
Figure 47. Power Good during DVS Transition ISHORT DC to DC converter
PGDVS = 1 Short−Circuit Protection

Power Good Delay PG Power Good

In order to generate a Reset signal, a delay can be
programmed between when the output voltage gets 93% of Individual bits generating interrupts will be set to 1 in the
its final value and when the Power Good pin is released to INT_ACK register (I2C read only registers), indicating the
a high level. interrupt source. INT_ACK register is automatically reset
by an I2C read. The INT_SEN register (read only register)
Vout contains real time indicators of interrupt sources.
When the host reads the INT_ACK registers the interrupt
register INT_ACK is cleared.
PG No
TOR[ 2:0 ]
Delay

SEN_TWARN
Delay Programmed in
TOR [2: 0] ACK_TWARN

I2C access on INT_ACK read read read read

Figure 48. Power Good Operation

Figure 49. TWARN Interrupt Operation Example

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 NCV6357

Configurations
Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request.
Below is the default configurations pre−defined:

Table 4. NCV6357 CONFIGURATION

5.0 A 5.0 A 5.0 A 5.0 A 5.0 A
Configuration NCV6357A NCV6357B NCV6357C NCV6357D NCV6357F
Default I2C address ADD1 – 14h: ADD2 – 18h: ADD1 – 14h: ADD2 – 18h: ADD4 – 60h:
PID product identification 0010100R/W 0011000R/W 0010100R/W 0011000R/W 1100100R/W
RID revision identification 21h 21h 21h 21h 21h
FID feature identification Metal Metal Metal Metal Metal
00h 01h 00h 08h 04h
Default VOUT – VSEL = 1 1.10 V 1.00 V 1.10 V 1.25 V 1.1 V
Default VOUT – VSEL = 0 1.80 V 0.90 V 1.80 V 1.25 V 1.0 V
Default MODE – VSEL = 1 Auto mode Forced PPWM Auto mode Auto mode Forced PPWM
Default MODE – VSEL = 0 Forced PPWM Forced PPWM Forced PPWM Forced PPWM Forced PPWM
Default IPEAK 6.8 A 6.8 A 6.8 A 6.8 A 6.8 A
Discharge path Activated Activated Not Activated Activated Activated
DVS 6.25 mV/2.666 ms 6.25 mV/0.666 ms 6.25 mV/2.666 ms 6.25 mV/0.666 ms 6.25 mV/0.666 ms
OPN NCV6357MTWAT NCV6357MTWB NCV6357MTWC NCV6357MTWD NCV6357MTWF
XG TXG TXG TXG TXG

Marking 6357A 6357B 6357C 6357D 6357F

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 NCV6357

I²C Compatible Interface

NCV6357 can support a subset of the I2C protocol as detailed below.

I2C Communication Description

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

START IC ADDRESS 1 ACK DATA 1 ACK DATA n /ACK STOP READ OUT FROM PART

1 à READ

/ACK
START IC ADDRESS 0 ACK DATA 1 ACK DATA n STOP WRITE INSIDE PART
ACK

If PART does not Acknolege, the /NACK will be followed by a STOP or Sr (repeated start).

0 à WRITE

Figure 50. General Protocol Description

The first byte transmitted is the Chip address (with the LSB bit set to 1 for a read operation, or set to 0 for a Write operation).
The following data will be:
• During a Write operation, the register address (@REG) is written in followed by the data. The writing process is
auto−incremental, so the first data will be written in @REG, the contents of @REG are incremented and the next data
byte is placed in the location pointed to by @REG + 1 …, etc
• During a Read operation, the NCV6357 will output the data from the last register that has been accessed by the last
write operation. Like the writing process, the reading process is auto−incremental.

Read Sequence
The Master will first make a “Pseudo Write” transaction with no data to set the internal address register. Then, a stop then
start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has pointed to:

FROM MCU to NCPxxxx

SETS INTERNAL
REGISTER POINTER

START IC ADDRESS 0 ACK REGISTER ADDRESS ACK STOP

0 à WRITE

START IC ADDRESS 1 ACK DATA 1 ACK DATA n /ACK STOP

REGISTER ADDRESS REGISTER ADDRESS + (n –1)

VALUE VALUE

n REGISTERS READ

1 à READ

Figure 51. Read Sequence

The first WRITE sequence will set the internal pointer to the register that is selected. Then the read transaction will start at
the address the write transaction has initiated.

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 NCV6357

Write Sequence
Write operation will be achieved by only one transaction. After chip address, the REG address has to be set, then following
data will be the data we want to write in REG, REG + 1, REG + 2, …, REG + n.

Write n Registers:

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

SETS INTERNAL WRITE VALUE IN WRITE VALUE IN
REGISTER POINTER REGISTER REG0 REGISTER REG0 + (n−1)
START IC ADDRESS 0 ACK REGISTER REG0 ADDRESS ACK REG VALUE ACK REG + (n – 1) VALUE ACK STOP

0 à WRITE

Figure 52. Write Sequence

Write then Read Sequence

With Stop Then Start

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

SETS INTERNAL WRITE VALUE IN WRITE VALUE IN
REGISTER POINTER REGISTER REG0 REGISTER REG0 + (n−1)
START IC ADDRESS 0 ACK REGISTER REG0 ADDRESS ACK REG VALUE ACK REG + (n – 1) VALUE ACK STOP

n REGISTERS WRITE

0 à WRITE

START IC ADDRESS 1 ACK DATA 1 ACK DATA k /ACK STOP

REGISTER REG + (n –1) REGISTER ADDRESS + (n –1) +

VALUE (k – 1) VALUE

k REGISTERS READ

1 à READ

Figure 53. Write Followed by Read Transaction

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 NCV6357

I2C Address
The NCV6357 has 8 available I2C addresses selectable by factory settings (ADD0 to ADD7). Different address settings can
be generated upon request to ON Semiconductor. See Table 5 (NCV6357 Configuration) for the default I2C address.

Table 5. I2C ADDRESS

I2C Address Hex A7 A6 A5 A4 A3 A2 A1 A0
ADD0 W 0x20 0 0 1 0 0 0 0 R/W
R 0x21
Add 0x10 −
ADD1 W 0x28 0 0 1 0 1 0 0 R/W
R 0x29
Add 0x14 −
ADD2 W 0x30 0 0 1 1 0 0 0 R/W
R 0x31
Add 0x18 −
ADD3 W 0x38 0 0 1 1 1 0 0 R/W
R 0x39
Add 0x1C −
ADD4 W 0xC0 1 1 0 0 0 0 0 R/W
R 0xC1
Add 0x60 −
ADD5 W 0xC8 1 1 0 0 1 0 0 R/W
R 0xC9
Add 0x64 −
ADD6 W 0xD0 1 1 0 1 0 0 0 R/W
R 0xD1
Add 0x68 −
ADD7 W 0xD8 1 1 0 1 1 0 0 R/W
R 0xD9
Add 0x6C −

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 NCV6357

Register Map
The tables below describe the I2C registers.

Registers / Bits Operations:

R Read only register
RC Read then Clear
RW Read and Write register
Reserved Address is reserved and register / bit is not physically designed

Table 6. I2C REGISTERS MAP CONFIGURATION (NCV6357A)

Register
Add. Name Type Def. Function
00h INT_ACK RC 00h Interrupt register
01h INT_SEN R 01h Sense register (real time status)
02h − − − Reserved for future use
03h PID R 20h Product Identification
04h RID R Metal Revision Identification
05h FID R 00h Features Identification (trim)
06h to 11h − − − Reserved for future use
12h PGOOD RW 11h Power good and active discharge settings (trim)
13h TIME RW 19h Enabling and DVS timings (trim)
14h COMMAND RW 8Dh Enabling and Operating mode Command register (trim)
15h − − − Reserved for future use
16h LIMCONF RW E3h Reset and limit configuration register (trim)
17h PROGVSEL1 RW 28 Output voltage settings for VSEL pin = High (trim)
18h PROGVSEL0 RW 60 Output voltage settings for VSEL pin = Low (trim)
19h to 26h − − − Reserved for future use
27h to FFh − − − Reserved. Test Registers

Table 7. I2C REGISTERS MAP CONFIGURATION (NCV6357B)

Register
Add. Name Type Def. Function
00h INT_ACK RC 00h Interrupt register
01h INT_SEN R 01h Sense register (real time status)
02h − − − Reserved for future use
03h PID R 20h Product Identification
04h RID R Metal Revision Identification
05h FID R 00h Features Identification (trim)
06h to 11h − − − Reserved for future use
12h PGOOD RW 11h Power good and active discharge settings (trim)
13h TIME RW 09h Enabling and DVS timings (trim)
14h COMMAND RW CD Enabling and Operating mode Command register (trim)
15h − − − Reserved for future use
16h LIMCONF RW E3h Reset and limit configuration register (trim)
17h PROGVSEL1 RW 20 Output voltage settings for VSEL pin = High (trim)
18h PROGVSEL0 RW 18 Output voltage settings for VSEL pin = Low (trim)
19h to 26h − − − Reserved for future use
27h to FFh − − − Reserved. Test Registers

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 NCV6357

Table 8. I2C REGISTERS MAP CONFIGURATION (NCV6357C)

Register
Add. Name Type Def. Function
00h INT_ACK RC 00h Interrupt register
01h INT_SEN R 01h Sense register (real time status)
02h − − − Reserved for future use
03h PID R 20h Product Identification
04h RID R Metal Revision Identification
05h FID R 00h Features Identification (trim)
06h to 11h − − − Reserved for future use
12h PGOOD RW 01h Power good and active discharge settings (trim)
13h TIME RW 19h Enabling and DVS timings (trim)
14h COMMAND RW 8Dh Enabling and Operating mode Command register (trim)
15h − − − Reserved for future use
16h LIMCONF RW E2h Reset and limit configuration register (trim)
17h PROGVSEL1 RW 28 Output voltage settings for VSEL pin = High (trim)
18h PROGVSEL0 RW 60 Output voltage settings for VSEL pin = Low (trim)
19h to 26h − − − Reserved for future use
27h to FFh − − − Reserved. Test Registers

Table 9. I2C REGISTERS MAP CONFIGURATION (NCV6357D)

Register
Add. Name Type Def. Function
00h INT_ACK RC 00h Interrupt register
01h INT_SEN R 01h Sense register (real time status)
02h − − − Reserved for future use
03h PID R 20h Product Identification
04h RID R Metal Revision Identification
05h FID R 08h Features Identification (trim)
06h to 11h − − − Reserved for future use
12h PGOOD RW 11h Power good and active discharge settings (trim)
13h TIME RW 09h Enabling and DVS timings (trim)
14h COMMAND RW 8Fh Enabling and Operating mode Command register (trim)
15h − − − Reserved for future use
16h LIMCONF RW E3h Reset and limit configuration register (trim)
17h PROGVSEL1 RW 34 Output voltage settings for VSEL pin = High (trim)
18h PROGVSEL0 RW 34 Output voltage settings for VSEL pin = Low (trim)
19h to 26h − − − Reserved for future use
27h to FFh − − − Reserved. Test Registers

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 NCV6357

Table 10. I2C REGISTERS MAP CONFIGURATION (NCV6357F)

Register
Add. Name Type Def. Function
00h INT_ACK RC 00h Interrupt register
01h INT_SEN R 01h Sense register (real time status)
02h − − − Reserved for future use
03h PID R 20h Product Identification
04h RID R Metal Revision Identification
05h FID R 04h Features Identification (trim)
06h to 11h − − − Reserved for future use
12h PGOOD RW 11h Power good and active discharge settings (trim)
13h TIME RW 09h Enabling and DVS timings (trim)
14h COMMAND RW 8Fh Enabling and Operating mode Command register (trim)
15h − − − Reserved for future use
16h LIMCONF RW E3h Reset and limit configuration register (trim)
17h PROGVSEL1 RW 28 Output voltage settings for VSEL pin = High (trim)
18h PROGVSEL0 RW 20 Output voltage settings for VSEL pin = Low (trim)
19h to 26h − − − Reserved for future use
27h to FFh − − − Reserved. Test Registers

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 NCV6357

Registers Description

Table 11. INTERRUPT ACKNOWLEDGE REGISTER

Name: INTACK Address: 00h
Type: RC Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7 D6 D5 D4 D3 D2 D1 D0
ACK_TSD ACK_TWARN ACK_TPREW Spare = 0 ACK_ISHORT ACK_UVLO ACK_IDCDC ACK_PG
Bit Bit Description
ACK_PG Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event detected
ACK_IDCDC DCDC Over Current Sense Acknowledgement
0: Cleared
1: DCDC Over Current Event detected
ACK_UVLO Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
ACK_ISHORT DCDC Short−Circuit Protection Sense Acknowledgement
0: Cleared
1: DCDC Short circuit protection detected
ACK_TPREW Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
ACK_TWARN Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
ACK_TSD Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected

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 NCV6357

Table 12. INTERRUPT SENSE REGISTER

Name: INTSEN Address: 01h
Type: R Default: 00000000b (00h)
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
SEN_TSD SEN_TWARN SEN_TPREW Spare = 0 SEN_ISHORT SEN_UVLO SEN_IDCDC SEN_PG
Bit Bit Description
SEN_PG Power Good Sense
0: DCDC Output Voltage below target
1: DCDC Output Voltage within nominal range
SEN_IDCDC DCDC over current sense
0: DCDC output current is below limit
1: DCDC output current is over limit
SEN_UVLO Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
SEN_ISHORT DCDC Short−Circuit Protection Sense
0: Short−Circuit detected not detected
1: Short−Circuit not detected
SEN_TPREW Thermal Pre−Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
SEN_TWARN Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
SEN_TSD Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit

Table 13. PRODUCT ID REGISTER

Name: PID Address: 03h
Type: R Default: 00011011b (21h)
Trigger: N/A Reset on N/A
D7 D6 D5 D4 D3 D2 D1 D0
PID_7 PID_6 PID_5 PID_4 PID_3 PID_2 PID_1 PID_0

Table 14. REVISION ID REGISTER

Name: RID Address: 04h
Type: R Default: Metal
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
RID_7 RID_6 RID_5 RID_4 RID_3 RID_2 RID_1 RID_0
Bit Bit Description
RID[7..0] Revision Identification
00000000: First Silicon

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 NCV6357

Table 15. FEATURE ID REGISTER

Name: FID Address: 05h
Type: R Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare Spare Spare Spare FID_3 FID_2 FID_1 FID_0
Bit Bit Description
FID[3..0] Feature Identification
00000000: NCV6357A 5.0 A, 1.80 V − 1.10 V configuration
00000001: NCV6357B 5.0 A, 0.90 V – 1.00 V configuration

Table 16. POWER GOOD REGISTER

Name: PGOOD Address: 12h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 0 Spare = 0 Spare = 0 DISCHG TOR[1..0] PGDVS PGDCDC
Bit Bit Description
PGDCDC Power Good Enabling
0 = Disabled
1 = Enabled
PGDVS Power Good Active On DVS
0 = Disabled
1 = Enabled
TOR[1..0] Time out Reset settings for Power Good
00 = 0 ms
01 = 8 ms
10 = 32 ms
11 = 64 ms
DISCHG Active discharge bit Enabling
0 = Discharge path disabled
1 = Discharge path enabled

Table 17. TIMING REGISTER

Name: TIME Address: 13h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
DELAY[2..0] DVS[1..0] Spare = 0 DBN_Time[1..0]
Bit Bit Description
DBN_Time[1..0] EN and VSEL debounce time
00 = No debounce
01 = 1−2 ms
10 = 2−3 ms
11 = 3−4 ms
DVS[1..0] DVS Speed
00 = 6.25 mV step / 0.333 ms
01 = 6.25 mV step / 0.666 ms
10 = 6.25 mV step / 1.333 ms
11 = 6.25 mV step / 2.666 ms
DELAY[2..0] Delay applied upon enabling (ms)
000b = 0 ms – 111b = 14 ms (Steps of 2 ms)

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 NCV6357

Table 18. COMMAND REGISTER

Name: COMMAND Address: 14h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
PPWMVSEL0 PPWMVSEL1 DVSMODE Sleep_Mode ENVSEL0 ENVSEL1 Spare VSELGT
Bit Bit Description
VSELGT VSEL Pin Gating
0 = Disabled
1 = Enabled
ENVSEL1 EN Pin Gating for VSEL internal signal = High
0: Disabled
1: Enabled
ENVSEL0 EN Pin Gating for VSEL internal signal = Low
0: Disabled
1: Enabled
Sleep_Mode Sleep mode
0 = Low Iq mode when EN and VSEL low
1 = Force product in sleep mode (when EN and VSEL are low)
DVSMODE DVS transition mode selection
0 = Auto
1 = Forced PPWM
PPWMVSEL1 Operating mode for MODE internal signal = High
0 = Auto
1 = Forced PPWM
PPWMVSEL0 Operating mode for MODE internal signal = Low
0 = Auto
1 = Forced PPWM

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 NCV6357

Table 19. LIMITS CONFIGURATION REGISTER

Name: LIMCONF Address: 16h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
IPEAK[1..0] TPWTH[1..0] Spare = 0 FORCERST RSTSTATUS REARM
Bit Bit Description
REARM Rearming of device after TSD / ISHORT
0: No re−arming after TSD / ISHORT
1: Re−arming active after TSD / ISHORT with no reset of I2C registers: new power−up sequence is initiated
with previously programmed I2C registers values
RSTSTATUS Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
FORCERST Force Reset Bit
0 = Default value. Self cleared to 0
1: Force reset of internal registers to default
TPWTH[1..0] Thermal pre−Warning threshold settings
00 = 83°C
01 = 94°C
10 = 105°C
11 = 116°C
IPEAK Inductor peak current settings
00 = 5.2 A (for 3.5 A output current)
01 = 5.8 A (for 4.0 A output current)
10 = 6.2 A (for 4.5 A output current)
11 = 6.8 A (for 5.0 A output current)

Table 20. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER

Name: PROGVSEL1 Address: 17h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
VoutVSEL1[7..0]
Bit Bit Description
VoutVSEL1[7..0] Sets the DC to DC converter output voltage when VSEL pin = 1 (and VSEL pin function is enabled in
register COMMAND.D0) or when VSEL pin function is disabled in register COMMAND.D0
0000000b = 0.6 V – 11011000 ~ 1111111b = 3.3 V (steps of 12.5 mV)

Table 21. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER

Name: PROGVSEL0 Address: 18h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
VoutVSEL0[7..0]
Bit Bit Description
VoutVSEL0[7..0] Sets the DC to DC converter output voltage when VSEL pin = 0 (and VSEL pin function is enabled in
register COMMAND.D0)
0000000b = 0.6 V – 11011000 ~ 1111111b = 3.3 V (steps of 12.5 mV)

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 NCV6357

APPLICATION INFORMATION

NCV6357
Supply Input
AVIN

4.7 mF PVIN
Core Supply Input
AGND

10 mF
Thermal
Protection

DCDC
5A
Enable Control EN SW
Input Operating
Modular 330 nH
Voltage VSEL Mode
Driver
Selection Control
2 × 22 mF

PG Output PGND
Power Good
Monitoring

FB
DCDC
GND Processor
I2C 2.4 MHz Sense
SDA Core
Processor I@C Controller
Control Interface GND
SCL

Figure 54. Typical Application Schematic

Output Filter Considerations Components Selection

The output filter introduces a double pole in the system at
a frequency of: Inductor Selection
The inductance of the inductor is chosen such that the
1
f LC + peak−to−peak ripple current IL_PP is approximately 20% to
2 p ǸL C (eq. 1)
50% of the maximum output current IOUT_MAX. This
The NCV6357 internal compensation network is
provides the best trade−off between transient response and
optimized for a typical output filter comprising a 330 nH
output ripple. The inductance corresponding to a given
inductor and 47 mF capacitor as describes in the basic
current ripple is:
application schematic in Figure 54.
(V IN * V OUT) V OUT
L+
Voltage Sensing Considerations V IN f SW I L_PP (eq. 2)
In order to regulate the power supply rail, the NCV6357 The selected inductor must have a saturation current
must sense its output voltage. The IC can support two rating higher than the maximum peak current which is
sensing methods: calculated by:
• Normal sensing: The FB pin should be connected to the I L_PP
output capacitor positive terminal (voltage to regulate) I L_MAX + I OUT_MAX )
2 (eq. 3)
• Remote sensing: The power supply rail sense should be
The inductor must also have a high enough current rating
made close to the system powered by the NCV6357.
to avoid self−heating. A low DCR is therefore preferred.
The voltage to the system is more accurate, since the
Refer to Table 22 for recommended inductors.
PCB line impedance voltage drop is within the
regulation loop. In this case, we recommend connecting
the FB pin to the system decoupling capacitor positive
terminal

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 NCV6357

Table 22. INDUCTOR SELECTION

Size (L y l y T) Saturation DCR Max
Supplier Part # Value (mH) (mm) Current Max (A) at 255C (mW)
Cyntec PIFE20161B−R33MS−11 0.33 2.0 × 1.6 × 1.2 4.0 33
Cyntec PIFE25201B−R33MS−11 0.33 2.5 × 2.0 × 1.2 5.2 17
Cyntec PIFE32251B−R33MS−11 0.33 3.2 × 2.5 × 1.2 6.5 14
TOKO DFE252012F−H−R33M 0.33 2.5 × 2.0 × 1.2 5.1 13
TOKO DFE201612E−H−R33M 0.33 2.0 × 1.6 × 1.2 4.8 21
TOKO FDSD0412−H−R33M 0.33 4.2 × 4.2 × 1.2 7.5 19
TDK VLS252012HBX−R33M 0.33 2.5 × 2.0 × 1.2 5.3 25
TDK SPM5030T−R35M 0.35 7.1 × 6.5 × 3.0 14.9 4
Chilisin HEI201612A−R24M−AUDG 0.24 2.0 × 1.6 × 1.2 4.8 13.5

Output Capacitor Selection I OUT_MAX (D * D 2) V OUT

The output capacitor selection is determined by output C IN_MIN + where D +
V IN_PP f SW V IN
voltage ripple and load transient response requirement. For
In addition, the input capacitor must be able to absorb the
high transient load performance a high output capacitor
input current, which has a RMS value of
value must be used. For a given peak−to−peak ripple current
IL_PP in the inductor of the output filter, the output voltage I +I ǸD * D2
IN_RMS OUT_MAX
ripple across the output capacitor is the sum of three The input capacitor also must be sufficient to protect the
components as shown below. device from over voltage spikes, and a 4.7 mF capacitor or
V OUT_PP [ V OUT_PP(C) ) V OUT_PP(ESR) ) V OUT_PP(ESL) greater is required. The input capacitor should be located as
With: close as possible to the IC. All PGND pins must be
I L_PP
connected together to the ground terminal of the input cap
V OUT_PP(C) +
8 C f SW
which then must be connected to the ground plane. All PVIN
pins must be connected together to the Vbat terminal of the
V OUT_PP(ESR) + I L_PP ESR input cap which then connects to the Vbat plane.
L ESL
V OUT_PP(ESL) +
L
V IN Power Capability
Where the peak−to−peak ripple current is given by The NCV6357’s power capability is driven by the
difference in temperature between the junction (TJ) and
(V IN * V OUT) V OUT
I L_PP + ambient (TA), the junction−to−ambient thermal resistance
V IN f SW L
(RqJA), and the on−chip power dissipation (PIC).
In applications with all ceramic output capacitors, the The on−chip power dissipation PIC can be determined as
main ripple component of the output ripple is VOUT_PP(C). PIC = PT − PL with the total power losses PT being
The minimum output capacitance can be calculated based on
a given output ripple requirement VOUT_PP in PPWM P T + V out I OUT ǒ1h * 1Ǔ
operation mode. where h is the efficiency and PL the simplified inductor
I L_PP
C MIN + power losses PL = I LOAD 2 x DCR .
8 V OUT_PP f SW
Now the junction temperature TJ can easily be calculated
as T J = R qJA x PIC + TA .
Input Capacitor Selection
Please note that the TJ should stay within the
One of the input capacitor selection requirements is the recommended operating conditions.
input voltage ripple. To minimize the input voltage ripple The RqJA is a function of the PCB layout (number of layers
and get better decoupling at the input power supply rail, a and copper and PCB size). For example, the NCV6357
ceramic capacitor is recommended due to low ESR and ESL. mounted on the EVB has a RqJA about 30°C/W.
The minimum input capacitance with respect to the input
ripple voltage VIN_PP is

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30
 NCV6357

Layout Considerations • PGND directly connected to Cin input capacitor, and

then connected to the GND plane: Local mini planes
Electrical Rules
used on the top layer (green) and the layer just below
Good electrical layout is key to proper operation, high
the top layer (yellow) with laser vias
efficiency, and noise reduction. Electrical layout guidelines
are: • SW connected to the Lout inductor with local mini
• Use wide and short traces for power paths (such as planes used on the top layer (green) and the layer just
below the top layer (yellow) with laser vias
PVIN, VOUT, SW, and PGND) to reduce parasitic
(See Figure 55 / 56 for example)
inductance and high−frequency loop area. It is also
good for efficiency improvement
• The device should be well decoupled by input capacitor
and the input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission
• SW track should be wide and short to reduce losses and
noise radiation
• It is recommended to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Try to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation
• Arrange a “quiet” path for output voltage sense, and
make it surrounded by a ground plane

Thermal Rules
Good PCB layout improves the thermal performance and
thus allows for high power dissipation even with a small IC
package. Thermal layout guidelines are:
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation
• Use multiple vias around the IC to connect the inner Figure 55. Placement Recommendation
ground layers to reduce thermal impedance
• Use a large and thick copper area especially in the top
layer for good thermal conduction and radiation
• Use two layers or more for the high current paths
(PVIN, PGND, SW) in order to split current into
different paths and limit PCB copper self−heating

Component Placement
• Input capacitor placed as close as possible to the IC
• PVIN directly connected to Cin input capacitor, and
then connected to the Vin plane. Local mini planes used
on the top layer (green) and the layer just below the top
layer (yellow) with laser vias
• AVIN connected to the Vin plane just after the capacitor
• AGND directly connected to the GND plane
Figure 56. Demo Board Example

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31
 NCV6357

Table 23. ORDERING INFORMATION

Device Marking Output Voltage Package Shipping†
NCV6357MTWATXG 6357A 5.0 A DFN 3.0 x 4.0 mm 3000 / Tape & Reel
1.80 V / 1.10 V (Pb−Free)
NCV6357MTWBTXG 6357B 5.0 A DFN 3.0 x 4.0 mm 3000 / Tape & Reel
0.90 V / 1.00 V (Pb−Free)
NCV6357MTWCTXG 6357C 5.0 A DFN 3.0 x 4.0 mm 3000 / Tape & Reel
1.80 V / 1.10 V (Pb−Free)
NCV6357MTWDTXG 6357D 5.0 A DFN 3.0 x 4.0 mm 3000 / Tape & Reel
1.25 V / 1.25 V (Pb−Free)
NCV6357MTWFTXG* 6357F 5.0 A DFN 3.0 x 4.0 mm 3000 / Tape & Reel
1.00 V / 1.10 V (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Not released yet.

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32
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