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Verilog SR Flip-Flop Code & Testbench

This document contains a Verilog module for an SR flip-flop (srflipflop) and a testbench module (test_srflipflop) to test it. The testbench initializes the clock and S/R inputs, applies different input patterns over time, and instantiates the srflipflop module being tested. It also sets input and output delay constraints on the ports.

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Meghana N
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42 views1 page

Verilog SR Flip-Flop Code & Testbench

This document contains a Verilog module for an SR flip-flop (srflipflop) and a testbench module (test_srflipflop) to test it. The testbench initializes the clock and S/R inputs, applies different input patterns over time, and instantiates the srflipflop module being tested. It also sets input and output delay constraints on the ports.

Uploaded by

Meghana N
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Code Testbench

`timescale 1ns/1ns `timescale 1ns/1ns


module srflipflop(clk,s,r,q,qbar); module test_srflipflop;
input clk,s,r; reg clk ;
output reg q,qbar; reg s,r;
wire q, qbar;
always @(clk,s,r)
begin srflipflop uut(clk,s,r,q,qbar);
if(clk==1) initial
begin begin
clk = 0; s = 1; r = 0; #10;
if(s==1'b0 && r==1'b1) clk = 1; s = 0; r = 1; #10;
begin clk = 1; s = 1; r = 0; #10;
q=0; clk = 1; s = 0; r = 0; #10;
qbar=~q; clk = 1; s = 1; r = 1; #10;
end end
endmodule
else if(s==1'b1 && r==1'b0)
begin constraints
q=1;
qbar=~q; set_input_delay -max 1.0 [get_port "clk"]
end set_input_delay -max 1.0 [get_port "s"]
set_input_delay -max 1.0 [get_port "r"]
else if(s==1'b0 && r==1'b0) set_output_delay -max 1.0 [get_port "q"]
begin set_output_delay -max 1.0 [get_port "qbar"]
q=q;
qbar=~q;
end

else if(s==1'b1 && r==1'b1)


begin
q=1'bz;
qbar= 1'bz;
end

end
end
endmodule

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