bq20z95

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SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION ENABLED WITH IMPEDANCE

TRACK™
Check for Samples: bq20z95

1FEATURES
2• Next Generation Patented Impedance Track™ DESCRIPTION
Technology Accurately Measures Available The bq20z95 SBS-compliant gas gauge and
Charge in Li-Ion and Li-Polymer Batteries protection IC is a single IC solution designed for
battery-pack or in-system installation. The bq20z95
– Better Than 1% Error Over Lifetime of the measures and maintains an accurate record of
Battery available charge in Li-Ion or Li-Polymer batteries
• Supports the Smart Battery Specification using its integrated high-performance analog
SBS V1.1 peripherals, monitors capacity change, battery
impedance, open-circuit voltage, and other critical
• Flexible Configuration for 2-Series to 4-Series
parameters of the battery pack as well and reports
Li-Ion and Li-Polymer Cells the information to the system host controller over a
• Powerful 8-Bit RISC CPU With Ultra-Low serial-communication bus. Together with the
Power Modes integrated analog front-end (AFE) short-circuit and
• Full Array of Programmable Protection overload protection, the bq20z95 maximizes
Features functionality and safety while minimizing external
component count, cost, and size in smart battery
– Voltage, Current, and Temperature circuits.
• Supports SHA-1 Authentication
The implemented Impedance Track™ gas gauging
• Complete Battery Protection and Gas Gauge technology continuously analyzes the battery
Solution in One Package impedance, resulting in superior gas-gauging
• Small 44-Pin TSSOP (DBT) Package accuracy. This enables remaining capacity to be
calculated with discharge rate, temperature, and cell
APPLICATIONS aging all accounted for during each stage of every
cycle with high accuracy.
• Notebook PCs
• Medical and Test Equipment
• Portable Instrumentation
Table 1. AVAILABLE OPTIONS
PACKAGE (1)
TA
44-PIN TSSOP (DBT) Tube 44-PIN TSSOP (DBT) Tape and Reel
–40°C to 85°C bq20z95DBT (2) bq20z95DBTR (3)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq20z95
SLUS757C – JULY 2007 – REVISED OCTOBER 2013 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SYSTEM PARTITIONING DIAGRAM

Pack +

ZVCHG

GPOD

PACK
SAFE
LED1

LED2

LED3

LED4

LED5

PFIN
¯¯¯¯

PMS

DSG

CHG

VCC

VSS
BAT
RBI
¯¯¯¯
DISP Fuse Blow Power Mode
Pre Charge FET N-Channel FET
LED Display Detection and Oscillator Control MSRT
¯¯¯¯¯
& PGOD Drive Drive
Logic

SMBD RESET
¯¯¯¯¯¯
SMBD
SMBC SMB 1.1 System Control AFE HW Control Watchdog ALERT
¯¯¯¯¯¯
SMBC

VCELL+
Data Flash Voltage Cell Voltage
Memory Measurement Multiplexer
VC1 VC1 VDD

VC2 VC2 OUT

VC3 VC3 CD

Over Over- & Under- Impedance VC4 VC4 GND

Charging
Temperature Voltage Track ™ Cell Balancing
Algorithm
Protection Protection Gas Gauging VC5
bq294xx

REG33
HW Over
SHA-1 Temperature Over Current Coloumb Current &
Regulators REG25
Authentication Measurement Protection Counter Short Circuit
Protection

bq20z95
GSRN

ASRN
GSRP

ASRP
TOUT

TS1

TS2

Pack -

RSNS
5mΩ – 20mΩ typ.

bq20z95
DBT Package
(TOP VIEW)

DSG 1 44 CHG
PACK 2 43 BAT
VCC 3 42 VC1
ZVCHG 4 41 VC2
GPOD 5 40 VC3
PMS 6 39 VC4
VSS 7 38 VC5
REG33 8 37 ASRP
TOUT 9 36 ASRN
VCELL+ 10 35 ¯¯¯¯¯¯
RESET
¯¯¯¯¯¯
ALERT 11 34 VSS
NC 12 33 RBI
TS1 13 32 REG25
TS2 14 31 VSS
¯¯¯¯¯
PRES 15 30 MRST
¯¯¯¯¯
¯¯¯¯
PFIN 16 29 GSRN
SAFE 17 28 GSRP
SMBD 18 27 LED5
NC 19 26 LED4
SMBC 20 25 LED3
¯¯¯¯
DISP 21 24 LED2
VSS 22 23 LED1

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TERMINAL FUNCTIONS
TERMINAL
I/O (1) DESCRIPTION
NO. NAME
1 DSG O High-side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in
2 PACK IA, P
SHUTDOWN mode.
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
3 VCC P
ensure device supply either from battery stack or battery pack input.
4 ZVCHG O P-chan pre-charge FET gate drive
High voltage general purpose open drain output. Can be configured to be used in pre-charge
5 GPOD OD
condition.
PRE-CHARGE mode setting input. Connect to PACK to enable 0-V pre-charge using charge FET
6 PMS I connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
8 REG33 P 3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
9 TOUT P Thermistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
10 VCELL+ —
VSS.
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
11 ALERT I/OD
be triggered.
12 NC — Not connected
13 TS1 IA Temperature sensor 1 input
14 TS2 IA Temperature sensor 2 input
15 PRES I/OD System/Host present input
16 PFIN I/OD Fuse blow detection input
17 SAFE I/OD Blow fuse signal output
18 SMBD I/OD SMBus data line
19 NC — Not connected
20 SMBC I/OD SMBus clock line
21 DISP I/OD Display enable input
22 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
23 LED1 I LED 1 current sink input
24 LED2 I LED 2 current sink input
25 LED3 I LED 3 current sink input
26 LED4 I LED 4 current sink input
27 LED5 I LED 5 current sink input
28 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor.
29 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor.
30 MRST I Reset input for internal CPU core. Connect to RESET for correct operation of device.
31 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
32 REG25 P 2.5-V regulator output. Connect at least a 1-μF capacitor to REG25 and VSS.
RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of
33 RBI P
short circuit condition.
34 VSS P Negative device power supply input. Connect all VSS pins together for operation of device.
35 RESET O Reset output. Connect to MSRT.
36 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor.
37 ASRP IA Short circuit and overload detection differential input. Connect to sense resistor.
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
38 VC5 IA, P
stack.
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
39 VC4 IA, P
negative voltage of the second lowest cell in cell stack.

(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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TERMINAL FUNCTIONS (continued)

TERMINAL
I/O (1) DESCRIPTION
NO. NAME
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
40 VC3 IA, P
cell stack and the negative voltage of the second highest cell in 4-series cell applications.
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
41 VC2 IA, P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2-cell stack
applications.
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
42 VC1 IA, P
stack in 4-cell applications. Connect to VC2 in 3- or 2-series cell applications.
43 BAT I, P Battery stack voltage sense input
44 CHG O High side N-chan charge FET gate drive

ABSOLUTE MAXIMUM RATINGS

(1)
Over Operating Free-Air Temperature (unless otherwise noted)
DESCRIPTION PIN UNIT
VBAT, VCC –0.3 V to 34 V
PACK, PMS –0.3 V to 34 V
VSS Supply voltage range VC(n)-VC(n+1); n = 1, 2, 3, 4 –0.3 V to 8.5 V
VC1, VC2, VC3, VC4 –0.3 V to 34 V
VC5 –0.3 V to 1 V
PFIN, SMBD, SMBC, LED1, LED2,
–0.3 V to 6 V
LED3, LED4, LED5, DISP
TS1, TS2, SAFE, VCELL+, PRES;
VIN Input voltage range –0.3 V to V(REG25) + 0.3 V
ALERT
MRST, GSRN, GSRP, RBI –0.3 V to V(REG25) + 0.3 V
ASRN, ASRP –1 V to 1 V
DSG, CHG, GPOD –0.3 V to 34 V
ZVCHG –0.3 V to V (BAT)
VOUT Output voltage range TOUT, ALERT, REG33 –0.3 V to 6 V
RESET –0.3 V to 7 V
REG25 –0.3 V to 2.75 V
PRES, PFIN, SMBD, SMBC, LED5,
ISS Maximum combined sink current for input pins 50 mA
LED4, LED3, LED2, LED1
TA Operating free-air temperature range –40°C to 85°C
TF Functional temperature –40°C to 100°C
Tstg Storage temperature range –65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
PARAMETER PIN MIN NOM MAX UNIT
VSS Supply voltage VCC, VBAT 4.5 25 V
V(STARTUP) Minimum startup voltage VCC, BAT, PACK 5.5 V
VC(n) – VC(n+1); n = 1,2,3,4 0 5 V
VC1, VC2, VC3, VC4 0 VSUP V
VIN Input Voltage Range VC5 0 0.5 V
ASRN, ASRP –0.5 0.5 V
PACK, PMS 0 25 V
V(GPOD) Output Voltage Range GPOD 0 25 V
A(GPOD) Drain Current (1) GPOD 1 mA
C(REG25) 2.5-V LDO Capacitor REG25 1 µF
C(REG33) 3.3-V LDO Capacitor REG33 2.2 µF
C(VCELL+) Cell Voltage Output Capacitor VCELL+ 0.1 µF
C(PACK) PACK input block resistor (2) PACK 1 kΩ

(1) Use an external resistor to limit the current to GPOD to 1mA in high voltage application.
(2) Use an external resistor to limit the inrush current PACK pin required.

ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I(NORMAL) Firmware running 550 µA
SLEEP Mode CHG FET on; DSG FET on 124 µA
I(SLEEP) CHG FET off; DSG FET on 90 µA
CHG FET off; DSG FET off 52 µA
I(SHUTDOWN) SHUTDOWN Mode 0.1 1 µA
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
I(PACK) Shutdown exit at VSTARTUP threshold 1 µA
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
Positive or negative wake threshold
V(WAKE) with 1.00 mV, 2.25 mV, 4.5 mV and 1.25 10 mV
9 mV programmable options
V(WAKE) = 1 mV;
-0.7 0.7
I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1
V(WAKE) = 2.25 mV;
I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1; -0.8 0.8
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0
V(WAKE_ACR) Accuracy of V(WAKE) mV
V(WAKE) = 4.5 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1; –1.0 1.0
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0
V(WAKE) = 9 mV;
–1.4 1.4
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1
Temperature drift of V(WAKE)
V(WAKE_TCO) 0.5 %/°C
accuracy
Time from application of current and
t(WAKE) 1 10 ms
wake of bq20z95
POWER-ON RESET
VIT– Negative-going voltage input Voltage at REG25 pin 1.70 1.80 1.90 V
Vhys Hysteresis VIT+ – VIT– 50 150 250 mV
tRST RESET active low time Active low time after power up or watchdog reset 100 250 560 µs
WATCHDOG TIMER
tWDTINT Watchdog start up detect time 250 500 1000 ms

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tWDWT Watchdog detect time 50 100 150 µs
2.5V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
V(REG25) Regulator output voltage I(REG25OUT) ≤ 16 mA; 2.41 2.5 2.59 V
TA = –40°C to 100°C
Regulator output change with I(REG25OUT) = 2 mA;
ΔV(REG25TEMP) ±0.2 %
temperature TA = –40°C to 100°C
5.4 < VCC or BAT < 25 V;
ΔV(REG25LINE) Line regulation 3 10 mV
I(REG25OUT) = 2 mA
0.2 mA ≤ I(REG25OUT) ≤ 2 mA 7 25
ΔV(REG25LOAD) Load Regulation mV
0.2 mA ≤ I(REG25OUT) ≤ 16 mA 25 50
Drawing current until
I(REG25MAX) Current Limit 5 40 75 mA
REG25 = 2 V to 0 V
3.3V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
V(REG33) Regulator output voltage I(REG33OUT) ≤ 25 mA; 3 3.3 3.6 V
TA = –40°C to 100°C
Regulator output change with I(REG33OUT) = 2 mA;
ΔV(REG33TEMP) ±0.2 %
temperature TA = –40°C to 100°C
5.4 < VCC or BAT < 25 V;
ΔV(REG33LINE) Line regulation 3 10 mV
I(REG33OUT) = 2 mA
0.2 mA ≤ I(REG33OUT) ≤ 2 mA 7 17
ΔV(REG33LOAD) Load Regulation mV
0.2mA ≤ I(REG33OUT) ≤ 25 mA 40 100
Drawing current until REG33 = 3 V 25 100 145
I(REG33MAX) Current Limit mA
Short REG33 to VSS, REG33 = 0 V 12 65
THERMISTOR DRIVE
V(TOUT) Output voltage I(TOUT) = 0 mA; TA = 25°C V(REG25) V
I(TOUT) = 1 mA; RDS(on) = (V(REG25) – V(TOUT))/1 mA; TA =
RDS(on) TOUT pass element resistance 50 100 Ω
–40°C to 100°C
VCELL+ HIGH VOLTAGE TRANSLATION
VC(n) – VC(n+1) = 0 V;
0.950 0.975 1
TA = –40°C to 100°C
V(VCELL+OUT)
VC(n) – VC(n+1) = 4.5 V;
0.275 0.3 0.375
TA = –40°C to 100°C
internal AFE reference voltage;
V(VCELL+REF) 0.965 0.975 0.985
Translation output TA = –40°C to 100°C V
0.98 × 1.02 ×
Voltage at PACK pin; V(PACK)/1
V(VCELL+PACK) V(PACK)/1 V(PACK)/1
TA = –40°C to 100°C 8
8 8
Voltage at BAT pin; 0.98 × 1.02 ×
V(VCELL+BAT) V(BAT)/18
TA = –40°C to 100°C V(BAT)/18 V(BAT)/18
CMMR Common mode rejection ratio VCELL+ 40 dB
K= {VCELL+ output (VC5=0 V; VC4=4.5 V) – VCELL+
0.147 0.150 0.153
output (VC5=0 V; VC4=0 V)}/4.5
K Cell scale factor K= {VCELL+ output (VC2=13.5V; VC1=18 V) – VCELL+
output 0.147 0.150 0.153
(VC5=13.5 V; VC1=13.5 V)}/4.5
VC(n) – VC(n+1) = 0V; VCELL+ = 0 V;
I(VCELL+OUT) Drive Current to VCELL+ capacitor 12 18 μA
TA = –40°C to 100°C
CELL output (VC2 = VC1 = 18 V) – CELL output (VC2 =
V(VCELL+O) CELL offset error –18 –1 18 mV
VC1 = 0 V)
IVCnL VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V –1 0.01 1 μA
CELL BALANCING
Internal cell balancing FET RDS(on) for internal FET switch at
RBAL 200 400 600 Ω
resistance VDS = 2 V; TA = 25°C

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
VOL = 25 mV (min) 15 25 35
OL detection threshold voltage
V(OL) VOL = 100 mV; RSNS = 0, 1 90 100 110 mV
accuracy
VOL = 205 mV (max) 185 205 225
V(SCC) = 50 mV (min) 30 50 70
SCC detection threshold voltage
V(SCC) V(SCC) = 200 mV; RSNS = 0, 1 180 200 220 mV
accuracy
V(SCC) = 475 mV (max) 428 475 523
V(SCD) = –50 mV (min) –30 –50 –70
SCD detection threshold voltage
V(SCD) V(SCD) = –200 mV; RSNS = 0, 1 –180 –200 –220 mV
accuracy
V(SCD) = –475 mV (max) –428 –475 –523
tda Delay time accuracy ±15.25 μs
tpd Protection circuit propagation delay 50 μs
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON) = V(DSG) – V(PACK); V(GS) = 10 MΩ; DSG and
V(DSGON) DSG pin output on voltage CHG on; 8 12 16 V
TA = –40°C to 100°C
V(CHGON) = V(CHG) – V(BAT); V(GS) = 10 MΩ; DSG and
V(CHGON) CHG pin output on voltage CHG on; 8 12 16 V
TA = –40°C to 100°C
V(DSGOFF) DSG pin output off voltage V(DSGOFF) = V(DSG) – V(PACK) 0.2 V
V(CHGOFF) CHG pin output off voltage V(CHGOFF) = V(CHG) – V(BAT) 0.2 V
CL= 4700 pF; V(PACK) ≤ DSG ≤ V(PACK) + 4V 400 1000
tr Rise time μs
CL= 4700 pF; V(BAT) ≤ CHG ≤ V(BAT) + 4V 400 1000
CL= 4700pF; V(PACK) + V(DSGON) ≤ DSG ≤ V(PACK) + 1V 40 200
tf Fall time μs
CL= 4700 pF; V(BAT) + V(CHGON) ≤ CHG ≤ V(BAT) + 1 V 40 200
V(ZVCHG) ZVCHG clamp voltage BAT = 4.5 V 3.3 3.5 3.7 V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
ALERT 60 100 200
R(PULLUP) Internal pullup resistance kΩ
RESET 1 3 6
ALERT 0.2
VOL Logic low output voltage level RESET; V(BAT) = 7V; V(REG25) = 1.5 V; I (RESET) = 200 μA 0.4 V
GPOD; I(GPOD) = 50 μA 0.6
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
VREG25–0
VOH Output voltage high (1) IL = –0.5 mA V
.5
VOL Low-level output voltage PRES, PFIN, ALERT, IL = 7 mA; 0.4 V
CI Input capacitance 5 pF
I(SAFE) SAFE source currents SAFE active, SAFE = V(REG25) –0.6 V –3 mA
Ilkg(SAFE) SAFE leakage current SAFE inactive –0.2 0.2 µA
Ilkg Input leakage current 1 µA
ADC (2)
Input voltage range TS1, TS2, using Internal Vref –0.2 1 V
Conversion time 31.5 ms
Resolution (no missing codes) 16 bits
Effective resolution 14 15 bits
Integral nonlinearity ±0.03 %FSR (3)

(1) RC[0:7] bus

(2) Unless otherwise specified, the specification limits are valid at all measurement speed modes.
(3) Full-scale reference
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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset error (4) 140 250 µV
Offset error drift (4) TA = 25°C to 85°C 2.5 18 μV/°C
Full-scale error (5) ±0.1% ±0.7%
Full-scale error drift 50 PPM/°C
Effective input resistance (6) 8 MΩ
COULOMB COUNTER
Input voltage range –0.20 0.20 V
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 bits
–0.1 V to 0.20 V ±0.007 ±0.034
Integral nonlinearity %FSR
–0.20 V to –0.1 V ±0.007
(7)
Offset error TA = 25°C to 85°C 10 µV
Offset error drift 0.4 2.45 µV/°C
Full-scale error (8) (9)
±0.35%
Full-scale error drift 150 PPM/°C
(10)
Effective input resistance TA = 25°C to 85°C 2.5 MΩ
INTERNAL TEMPERATURE SENSOR
V(TEMP) Temperature sensor voltage (11) –2.0 mV/°C
VOLTAGE REFERENCE
Output voltage 1.215 1.225 1.230 V
Output voltage drift 65 PPM/°C
HIGH FREQUENCY OSCILLATOR
f(OSC) Operating frequency 4.194 MHz

(12) (13)
–3% 0.25% 3%
f(EIO) Frequency error
TA = 20°C to 70°C –2% 0.25% 2%
t(SXO) Start-up time (14) 2.5 5 ms
LOW FREQUENCY OSCILLATOR
f(LOSC) Operating frequency 32.768 kHz
–2.5% 0.25% 2.5%
f(LEIO) Frequency error (13) (15)
TA = 20°C to 70°C –1.5% 0.25% 1.5%
t(LSXO) Start-up time (14) 500 µs

(4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference
(5) Uncalibrated performance. This gain error can be eliminated with external calibration.
(6) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(7) Post-calibration performance
(8) Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
(9) Uncalibrated performance. This gain error can be eliminated with external calibration.
(10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(11) –53.7 LSB/°C
(12) The frequency error is measured from 4.194 MHz.
(13) The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5V, TA = 25°C.
(14) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
(15) The frequency error is measured from 32.768 kHz.

DATA FLASH CHARACTERISTICS (Over Recommended Operating Temperature and Supply

Voltage)
Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)

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DATA FLASH CHARACTERISTICS (Over Recommended Operating Temperature and Supply

Voltage) (continued)
Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming write-cycles 20k Cycles
(1)
t(ROWPROG) Row programming time See 2 ms
t(MASSERASE) Mass-erase time 200 ms
t(PAGEERASE) Page-erase time 20 ms
I(DDPROG) Flash-write supply current 5 10 mA
I(DDERASE) Flash-erase supply current 5 10 mA
RAM BACKUP
V(RBI) > V(RBI)MIN, VREG25 < VIT–,
1000 2500
TA = 85°C
I(RB) RB data-retention input current nA
V(RBI) > V(RBI)MIN, VREG25 < VIT–,
90 220
TA = 25°C
V(RB) RB data-retention input voltage (1) 1.7 V

(1) Specified by design. Not production tested.

SMBUS TIMING CHARACTERISTICS

TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(SMB) SMBus operating frequency SLAVE mode, SMBC 50% duty cycle 10 100 kHz
f(MAS) SMBus master clock frequency MASTER mode, No clock low slave extend 51.2 kHz
Bus free time between start and stop
t(BUF) 4.7 µs
(see Figure 1)
t(HD:STA) Hold time after (repeated) start (see 4 µs
Figure 1)
t(SU:STA) Repeated start setup time (see Figure 1) 4.7 µs
t(SU:STO) Stop setup time (see Figure 1) 4 µs
t(HD:DAT) RECEIVE mode 0 ns
Data hold time (see Figure 1)
TRANSMIT mode 300
t(SU:DAT) Data setup time (see Figure 1) 250 ns
(1)
t(TIMEOUT) Error signal/detect (see Figure 1) See 25 35 µs
t(LOW) Clock low period (see Figure 1) 4.7 µs
(2)
t(HIGH) Clock high period (see Figure 1) See 4 50 µs
(3)
t(LOW:SEXT) Cumulative clock low slave extend time See 25 µs
Cumulative clock low master extend time (4)
t(LOW:MEXT) See 10 µs
(see Figure 1)
(5)
tf Clock/data fall time See 300 ns
(6)
tr Clock/data rise time See 1000 ns

(1) The bq20z95 times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z95 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tf = 0.9VDD to (VILMAX – 0.15)

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TLOW TR TF THD:STA
SCLK

THD:STA THIGH TSU:STA TSU:STO

THD:DAT TSU:DAT

SDATA

TBUF
P S S P
Start Stop
TLOW:SEXT
SCLK ACK† SCLK ACK†
TLOW:MEXT TLOW:MEXT TLOW:MEXT

SCLK

SDATA

A. SCLKACK is the acknowledge-related clock pulse generated by the master.

Figure 1. SMBus Timing Diagram

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FEATURE SET

Primary (1st Level) Safety Features

The bq20z95 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
• Cell over/undervoltage protection
• Charge and discharge overcurrent
• Short circuit
• Charge and discharge overtemperature
• AFE watchdog

Secondary (2nd Level) Safety Features

The secondary safety features of the bq20z95 can be used to indicate more serious faults via the SAFE (pin 7).
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. The secondary safety protection features include:
• Safety overvoltage
• Safety overcurrent in Charge and Discharge
• Safety overtemperature in Charge and Discharge
• Charge FET and 0-V Charge FET fault
• Discharge FET fault
• AFE communication fault

Charge Control Features

The bq20z95 charge control features include:
• Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
• Determines the chemical state of charge of each battery cell using Impedance Track and can reduce the
charge difference of the battery cells in fully charged state of the battery pack gradually using cell balancing
algorithm during charging. This prevents fully charged cells from overcharging and causing excessive
degradation and also increases the usable pack energy by preventing premature charge termination
• Supports pre-charging/zero-volt charging
• Support fast charging
• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
• Reports charging fault and also indicate charge status via charge and discharge alarms.

Gas Gauging
The bq20z95 uses the Impedance Track technology to measure and calculate the available charge in battery
cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge
discharge learning cycle required.
See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364)
for further details.

Authentication
The bq20z95 supports authentication by the host using SHA-1.

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Power Modes
The bq20z95 supports three power modes to reduce power consumption:
• In NORMAL mode, the bq20z95 performs measurements, calculations, protection decisions and data updates
in 1-s intervals. Between these intervals, the bq20z95 is in a reduced power stage.
• In SLEEP mode, the bq20z95 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq20z95 is in a reduced power stage. The bq20z95
has a wake function that enables exit from SLEEP mode when current flow or failure is detected.
• In SHUTDOWN mode the bq20z95 is completely disabled.

CONFIGURATION

Oscillator Function
The bq20z95 fully integrates the system oscillators. Therefore, the bq20z95 requires no external components for
this feature.

System Present Operation

The bq20z95 checks the PRES pin periodically (1s). If PRES input is pulled to ground by external system, the
bq20z95 detects this as system present.

BATTERY PARAMETER MEASUREMENTS

The bq20z95 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage and temperature measurement.

Charge and Discharge Counting

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq20z95 detects charge activity when VSR = V(SRP) – V(SRN)is positive and
discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq20z95 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.

Voltage
The bq20z95 updates the individual series cell voltages at 1-s intervals. The internal ADC of the bq20z95
measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the Impedance Track gas-gauging.

Current
The bq20z95 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5-mΩ to 20-mΩ typ. sense resistor.

Auto Calibration
The bq20z95 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq20z95 performs auto-calibration when the SMBus lines stay
low continuously for a minimum of 5 s.

Temperature
The bq20z95 has an internal temperature sensor and two external temperature sensor inputs TS1 and TS2 used
in conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the battery environmental
temperature. The bq20z95 can be configured to use internal or up to two external temperature sensors.

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COMMUNICATIONS
The bq20z95 uses SMBus v1.1 with MASTER mode and package error checking (PEC) options per the SBS
specification.

SMBus On and Off State

The bq20z95 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.

SBS Commands

Table 2. SBS COMMANDS

SBS Size in Min Max Default
Mode Name Format Unit
Cmd Bytes Value Value Value
0x00 R/W ManufacturerAccess hex 2 0x0000 0xffff —
0x01 R/W RemainingCapacityAlarm unsigned int 2 0 65535 — mAh or
10 mWh
0x02 R/W RemainingTimeAlarm unsigned int 2 0 65535 — min
0x03 R/W BatteryMode hex 2 0x0000 0xffff —
0x04 R/W AtRate signed int 2 –32768 32767 — mA or 10
mW
0x05 R AtRateTimeToFull unsigned int 2 0 65535 — min
0x06 R AtRateTimeToEmpty unsigned int 2 0 65535 — min
0x07 R AtRateOK unsigned int 2 0 65535 —
0x08 R Temperature unsigned int 2 0 65535 — 0.1°K
0x09 R Voltage unsigned int 2 0 20000 — mV
0x0a R Current signed int 2 –32768 32767 — mA
0x0b R AverageCurrent signed int 2 –32768 32767 — mA
0x0c R MaxError unsigned int 1 0 100 — %
0x0d R RelativeStateOfCharge unsigned int 1 0 100 — %
0x0e R AbsoluteStateOfCharge unsigned int 1 0 100 — %
0x0f R/W RemainingCapacity unsigned int 2 0 65535 — mAh or
10 mWh
0x10 R FullChargeCapacity unsigned int 2 0 65535 — mAh or
10 mWh
0x11 R RunTimeToEmpty unsigned int 2 0 65535 — min
0x12 R AverageTimeToEmpty unsigned int 2 0 65535 — min
0x13 R AverageTimeToFull unsigned int 2 0 65535 — min
0x14 R ChargingCurrent unsigned int 2 0 65535 — mA
0x15 R ChargingVoltage unsigned int 2 0 65535 — mV
0x16 R BatteryStatus unsigned int 2 0x0000 0xffff —
0x17 R/W CycleCount unsigned int 2 0 65535 —
0x18 R/W DesignCapacity unsigned int 2 0 65535 — mAh or
10 mWh
0x19 R/W DesignVoltage unsigned int 2 7000 16000 14400 mV
0x1a R/W SpecificationInfo unsigned int 2 0x0000 0xffff 0x0031
0x1b R/W ManufactureDate unsigned int 2 0 65535 0
0x1c R/W SerialNumber hex 2 0x0000 0xffff 0x0001
0x20 R/W ManufacturerName String 11+1 — — Texas ASCII
Instruments
0x21 R/W DeviceName String 7+1 — — bq20z95 ASCII
0x22 R/W DeviceChemistry String 4+1 — — LION ASCII
0x23 R ManufacturerData String 14+1 — — — ASCII

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Table 2. SBS COMMANDS (continued)

SBS Size in Min Max Default
Mode Name Format Unit
Cmd Bytes Value Value Value
0x2f R/W Authenticate String 20+1 — — — ASCII
0x3c R CellVoltage4 unsigned int 2 0 65535 — mV
0x3d R CellVoltage3 unsigned int 2 0 65535 — mV
0x3e R CellVoltage2 unsigned int 2 0 65535 — mV
0x3f R CellVoltage1 unsigned int 2 0 65535 — mV

Table 3. EXTENDED SBS COMMANDS

SBS Size in Default
Mode Name Format Min Value Max Value Unit
Cmd Bytes Value
0x45 R AFEData String 11+1 — — — ASCII
0x46 R/W FETControl hex 1 0x00 0xff —
0x4f R StateOfHealth unsigned int 1 0 100 — %
0x51 R SafetyStatus hex 2 0x0000 0xffff —
0x53 R PFStatus hex 2 0x0000 0xffff —
0x54 R OperationStatus hex 2 0x0000 0xffff —
0x55 R ChargingStatus hex 2 0x0000 0xffff —
0x57 R ResetData hex 2 0x0000 0xffff —
0x5a R PackVoltage unsigned int 2 0 65535 — mV
0x5d R AverageVoltage unsigned int 2 0 65535 — mV
0x60 R/W UnSealKey hex 4 0x00000000 0xffffffff —
0x61 R/W FullAccessKey hex 4 0x00000000 0xffffffff —
0x62 R/W PFKey hex 4 0x00000000 0xffffffff —
0x63 R/W AuthenKey3 hex 4 0x00000000 0xffffffff —
0x64 R/W AuthenKey2 hex 4 0x00000000 0xffffffff —
0x65 R/W AuthenKey1 hex 4 0x00000000 0xffffffff —
0x66 R/W AuthenKey0 hex 4 0x00000000 0xffffffff —
0x70 R/W ManufacturerInfo String 31+1 — — —
0x71 R/W SenseResistor unsigned int 2 0 65535 — μΩ
0x77 R/W DataFlashSubClassID hex 2 0x0000 0xffff —
0x78 R/W DataFlashSubClassPage1 hex 32 — — —
0x79 R/W DataFlashSubClassPage2 hex 32 — — —
0x7a R/W DataFlashSubClassPage3 hex 32 — — —
0x7b R/W DataFlashSubClassPage4 hex 32 — — —
0x7c R/W DataFlashSubClassPage5 hex 32 — — —
0x7d R/W DataFlashSubClassPage6 hex 32 — — —
0x7e R/W DataFlashSubClassPage7 hex 32 — — —
0x7f R/W DataFlashSubClassPage8 hex 32 — — —

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Application Schematic

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 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

BQ20Z95DBT NRND TSSOP DBT 44 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 20Z95DBT
& no Sb/Br)
BQ20Z95DBTR NRND TSSOP DBT 44 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 20Z95DBT
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ20Z95DBTR TSSOP DBT 44 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ20Z95DBTR TSSOP DBT 44 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBT0044A SCALE 1.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6
TYP
6.2 C
A PIN 1 INDEX 0.1 C
AREA
42X 0.5
44
1

2X
11.1 10.5
10.9
NOTE 3

22
23
0.27
44X 1.2 MAX
4.5 0.17
B
4.3 0.08 C A B
NOTE 4

0.25
GAGE PLANE
0.15
0.05

(0.15) TYP

SEE DETAIL A 0.75

0 -8 0.50
DETAIL A
A 20

TYPICAL

4220223/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBT0044A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SYMM
44X (1.5)

1 (R0.05) TYP
44

44X (0.3)

42X (0.5)

SYMM

22 23

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220223/A 02/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBT0044A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

44X (1.5) SYMM

(R0.05) TYP
1
44

44X (0.3)

42X (0.5)

SYMM

22 23

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X

4220223/A 02/2017
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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