SN54221, SN54LS221, SN74221, SN74LS221 Dual Monostable Multivibrators With Schmitt-Trigger Inputs
SN54221, SN54LS221, SN74221, SN74LS221 Dual Monostable Multivibrators With Schmitt-Trigger Inputs
                                                                                                                                    1R ext /Cext
                                                  OUTPUT
                                                   PULSE
                              TYPE               LENGTH(S)
                                                                                                                                    VCC
                                                                                                                                    NC
                                                                                                                                    1B
                                                                                                                                    1A
                          SN54221                       21
                          SN74221                       28
                                                                                                                                    3 2 1 20 19
                          SN54LS221                     49                                                        1CLR         4               18                1Cext
                                                                                                                    1Q         5                         17      1Q
                          SN74LS221                     70
                                                                                                                    NC         6                         16      NC
                                                                                                                    2Q         7                         15      2Q
description                                                                                                       2Cext        8                   14            2CLR
                                                                                                                                       9 10 11 12 13
         The ’221 and ’LS221 devices are monolithic dual
         multivibrators with performance characteristics
                                                                                                                                                  2A
                                                                                                                                                  2B
                                                                                                                                                  NC
                                                                                                                                                 GND
         virtually identical to those of the ’121 devices.                                                                         2R ext/Cext
         Each multivibrator features a negative-transition-
         triggered input and a positive-transition-triggered
         input, either of which can be used as an inhibit                                                         NC – No internal connection
         input.
         Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
         pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
         transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
         immunity to VCC noise, typically of 1.5 V, is also provided by internal latching circuitry.
         Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
         components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
         relative to the output pulse. Output pulse length can be varied from 35 ns to the maximums shown in the above
         table by choosing appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of
         30 ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL
         compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of
         the switching characteristics waveforms.
         Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and
         temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
                    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
                    Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.                                                               Copyright  1998, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments                                                        On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include                                                        unless otherwise noted. On all other products, production
testing of all parameters.                                                                                                   processing does not necessarily include testing of all parameters.
description (continued)
     Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
     capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,
     2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).
     Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In
     circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ
     can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
     temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
     duty cycles are available if a certain amount of pulse-width jitter is allowed.
     The variance in output pulse width from device to device typically is less than ±0.5% for given external timing
     components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
     versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
     Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
     so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
     merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.
     The SN54221 and SN54LS221 are characterized for operation over the full military temperature range of –55°C
     to 125°C. The SN74221 and SN74LS221 are characterized for operation from 0°C to 70°C.
                                                     FUNCTION TABLE
                                               (each monostable multivibrator)
                                                    INPUTS                 OUTPUTS
                                             CLR       A           B       Q        Q
                                               L       X           X       L        H
                                               X       H           X       L        H
                                               X       X           L       L        H
                                              H        L           ↑           †        †
                                              H        ↓           H           †        †
                                              ↑‡       L           H           †        †
                                           † Pulsed-output patterns are tested during
                                             AC switching at 25°C with Rext = 2 kΩ, and
                                             Cext = 80 pF.
                                           ‡ This condition is true only if the output of
                                             the latch formed by the two NAND gates
                                             has been conditioned to the logic 1 state
                                             prior to CLR going high. This latch is
                                             conditioned by taking either A high or
                                             B low while CLR is inactive (high).
logic symbol†
                                              1                     &
                                        1A                                    1
                                              2
                                        1B                                                          13
                                                                                                         1Q
                                              3
                                     1CLR                      R                                    4
                                              14                                                         1Q
                                     1Cext                     CX
                                              15
                               1Rext/Cext                      RX/CX
                                              9
                                        2A                          &         1
                                              10
                                        2B                                                          5
                                                                                                         2Q
                                              11
                                     2CLR                      R
                                                                                                    12
                                              6                                                          2Q
                                     2Cext                     CX
                                              7
                               2Rext/Cext                      RX/CX
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
Rext
                                                           To Cext      To Rext/Cext
                                                           Terminal       Terminal
NOTE: Due to the internal circuit, the Rext/Cext terminal is never more positive than the Cext terminal.
                          VCC                                                                    VCC
                                           Req                                100 Ω NOM
Input
Output
SN54/74LS221
                         VCC                                                                     VCC
                                           Req                                                 120 Ω NOM
Input
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
       Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
       Input voltage range, VI (see Note 1): ’LS221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
                                                ’221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
       Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
                                                                    DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W
                                                                    N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
       Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
  functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
  implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
           2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
               length of zero
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
                                                                                                         SN54221          SN74221
                                                                                                                                         UNIT
                                                                                                         MIN    MAX       MIN    MAX
                                                                               A or B input               50               50
    tw      Pulse duration                                                                                                                ns
                                                                               CLR                        20               20
    tsu     Setup time, inactive-state¶                                        CLR                        15               15             ns
    Rext    External timing resistance                                                                   1.4*     30*      1.4      40   kΩ
    Cext    External timing capacitance                                                                    0*   1000*       0    1000    µF
                                                                               Rext = 2 kΩ                       67%             67%
            Output duty cycle
                                                                               Rext = MAX Rext                   90%             90%
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶ Inactive-state setup time is also referred to as recovery time.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
                                                                                                         SN54LS221      SN74LS221
                                                                                                                                      UNIT
                                                                                                         MIN    MAX     MIN    MAX
                                                                                  A or B                   50            50
    tw      Pulse duration                                                                                                             ns
                                                                                  CLR                      40            40
    tsu     Setup time, inactive state¶                                           CLR                      15            15            ns
    Rext    External timing resistance                                                                   1.4*     70*    1.4    100   kΩ
    Cext    External timing capacitance                                                                    0*   1000*     0    1000   µF
                                                                                  RT = 2 kΩ                      50%           50%
            Output duty cycle
                                                                                  RT = MAX Rext                  90%           90%
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶ Inactive-state setup time is also referred to as recovery time.
                                                                                                3V
               B†
                                                                                                0V
                                     ≥ 60 ns
                                                                                                3V
              CLR
                                                                                                0V
                                                                                                VOH
                Q
                                                                                                VOL
                                                                                                3V
               B†
                                                                                                0V
                                 ≥ 50 ns                                                tsu
                                                                        ≥0
                                                                                                3V
              CLR
                                                                                                0V
                                                                                           tw
                     Triggered
                                                                                                VOH
                Q
                                                                                                VOL
                     Not Triggered
                                 CONDITION 3: CLR OVERRIDING B, THEN TRIGGER FROM B
† A is low.
                                                                                                                       VOH
                 Q
                                                                                                                       VOL
                                       tw
                                                                                                                      3V
                A‡
                                                                                                                      0V
                                      ≥ 60 ns
                                                                                                                      3V
              CLR
                                                                                                                      0V
                                        tPLH                       tPHL
                                                                                                                      VOH
                 Q
                                                                                                                      VOL
                                            tPHL                        tPLH
                                                                                                                      VOH
                 Q
                                                                                                                      VOL
                                                                                                                      3V
                A‡
                                                                                                                      0V
                                                                   tw
                                                                                                                      VOH
                 Q
                                                                                                                      VOL
                                                                     tw
                                                                                                                      VOH
                 Q
                                                                                                                      VOL
RL
     From Output
                                                      (see Note B)
       Under Test                                                                    High-Level
                        CL = 15 pF
                                                                                          Pulse
                      (see Note A)
tw
                                                                                     Low-Level
                                                                                         Pulse
                            LOAD CIRCUIT FOR
                                BI-STATE                                                                  VOLTAGE WAVEFORMS
                          TOTEM-POLE OUTPUTS                                                               PULSE DURATIONS
                                                                                                                                  3V
                                                                                           Input
                                                                                                                                  0V
                                                                                                   tPLH                        tPHL
0.5
                                                                                                                                                                                                               tw ≈ 420 ns
                                                                                                                                                                     0                                         at VCC = 5 V
– 0.5
                                                            Median                Median
                                                            +0.5%                 +0.5%
                                                                                                                                                                 –1
                                                                                                                                                                   4.5                4.75            5        5.25           5.5
                                                                         Median
                                                                                                                                                                                         VCC – Supply Voltage – V
                                                                   tw – Output Pulse
                                                                   Figure 3                                                                                                                    Figure 4
                                                                                                                                                                          Cext = 0.1 µ F
                                             0.5
                                                                                                                                                    100 µs
                                                                                                                t w – Output Pulse
                                                                                                                                                                          Cext = 0.01 µ F
                                                                                       tw ≈ 420 ns
                                               0                                       at TA = 25°C                                                           10 µs
                                                                                                                                                                          Cext = 1000 pF
                                                                                                                                                               1 µs
                                            – 0.5                                                                                                                         Cext = 100 pF
                                                                                                                                                100 ns                                Cext = 10 pF
                                                                                                                                                                          VCC = 5 V                        See Note A
                                                                                                                                                                          TA = 25°C
                                              –1                                                                                                              10 ns
                                                –75 –50    –25      0      25     50    75    100     125                                                             1        2           4      7 10    20        40   70 100
                                                          TA – Free-Air Temperature – °C                                                                                        Rext – Timing Resistor Value – kΩ
                                                                   Figure 5                                                                                                                    Figure 6
† Data for temperatures below 0°C and above 70°C, and for supply voltages below 4.75 V and above 5.25 V are applicable for the SN54221 only.
NOTE A: These values of resistance exceed the maximum recommended for use over the full military temperature range of the SN54221.
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