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TL431, TL432
SLVS543P – AUGUST 2004 – REVISED NOVEMBER 2018

TL431 / TL432 Precision Programmable Reference

1 Features 3 Description
1• Reference Voltage Tolerance at 25°C The TL431LI / TL432LI are pin-to-pin alternatives
to TL431 / TL432. TL43xLI offers better stability,
– 0.5% (B Grade) lower temperature drift (VI(dev)), and lower
– 1% (A Grade) reference current (Iref) for improved system
– 2% (Standard Grade) accuracy.
• Adjustable Output Voltage: Vref to 36 V The TL431 and TL432 devices are three-terminal
• Operation From −40°C to 125°C adjustable shunt regulators, with specified thermal
stability over applicable automotive, commercial, and
• Typical Temperature Drift (TL43xB)
military temperature ranges. The output voltage can
– 6 mV (C Temp) be set to any value between Vref (approximately
– 14 mV (I Temp, Q Temp) 2.5 V) and 36 V, with two external resistors. These
• Low Output Noise devices have a typical output impedance of 0.2 Ω.
Active output circuitry provides a very sharp turn-on
• 0.2-Ω Typical Output Impedance characteristic, making these devices excellent
• Sink-Current Capability: 1 mA to 100 mA replacements for Zener diodes in many applications,
such as onboard regulation, adjustable power
2 Applications supplies, and switching power supplies. The TL432
device has exactly the same functionality and
• Adjustable Voltage and Current Referencing electrical specifications as the TL431 device, but has
• Secondary Side Regulation in Flyback SMPSs different pinouts for the DBV, DBZ, and PK packages.
• Zener Replacement Both the TL431 and TL432 devices are offered in
• Voltage Monitoring three grades, with initial tolerances (at 25°C) of 0.5%,
• Comparator with Integrated Reference 1%, and 2%, for the B, A, and standard grade,
respectively. In addition, low output drift versus
Simplified Schematic temperature ensures good stability over the entire
temperature range.
Input VKA
The TL43xxC devices are characterized for operation
IKA
from 0°C to 70°C, the TL43xxI devices are
characterized for operation from –40°C to 85°C, and
the TL43xxQ devices are characterized for operation
from –40°C to 125°C.
Vref
Device Information(1)
PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)
SOT-23-3 (3) 2.90 mm × 1.30 mm
SOT-23-5 (5) 2.90 mm × 1.60 mm
TL43x SOIC (8) 4.90 mm × 3.90 mm
PDIP (8) 9.50 mm × 6.35 mm
SOP (8) 6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL431, TL432
SLVS543P – AUGUST 2004 – REVISED NOVEMBER 2018 www.ti.com

Table of Contents
1 Features .................................................................. 1 9 Detailed Description ............................................ 20
2 Applications ........................................................... 1 9.1 Overview ................................................................. 20
3 Description ............................................................. 1 9.2 Functional Block Diagram ....................................... 20
4 Revision History..................................................... 2 9.3 Feature Description................................................. 21
9.4 Device Functional Modes........................................ 21
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 4 10 Applications and Implementation...................... 22
10.1 Application Information.......................................... 22
7 Specifications......................................................... 5
10.2 Typical Applications .............................................. 22
7.1 Absolute Maximum Ratings ...................................... 5
10.3 System Examples ................................................. 27
7.2 ESD Ratings.............................................................. 5
7.3 Thermal Information .................................................. 5 11 Power Supply Recommendations ..................... 30
7.4 Recommended Operating Conditions....................... 5 12 Layout................................................................... 30
7.5 Electrical Characteristics, TL431C, TL432C ............. 6 12.1 Layout Guidelines ................................................. 30
7.6 Electrical Characteristics, TL431I, TL432I ................ 7 12.2 Layout Example .................................................... 30
7.7 Electrical Characteristics, TL431Q, TL432Q............. 8 13 Device and Documentation Support ................. 31
7.8 Electrical Characteristics, TL431AC, TL432AC ........ 9 13.1 Device Nomenclature............................................ 31
7.9 Electrical Characteristics, TL431AI, TL432AI ......... 10 13.2 Related Links ........................................................ 31
7.10 Electrical Characteristics, TL431AQ, TL432AQ.... 11 13.3 Receiving Notification of Documentation Updates 31
7.11 Electrical Characteristics, TL431BC, TL432BC .... 12 13.4 Community Resources.......................................... 31
7.12 Electrical Characteristics, TL431BI, TL432BI ....... 13 13.5 Trademarks ........................................................... 31
7.13 Electrical Characteristics, TL431BQ, TL432BQ.... 14 13.6 Electrostatic Discharge Caution ............................ 32
7.14 Typical Characteristics .......................................... 15 13.7 Glossary ................................................................ 32
8 Parameter Measurement Information ................ 19 14 Mechanical, Packaging, and Orderable
Information ........................................................... 32

4 Revision History
Changes from Revision O (January 2015) to Revision P Page

• Added text to the Description section..................................................................................................................................... 1

• Added TL43x Device Comparison Table ............................................................................................................................... 3
• Added TL43x Device Nomenclature section ........................................................................................................................ 31

Changes from Revision N (January 2014) to Revision O Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
• Added Applications. ................................................................................................................................................................ 1
• Moved Typical Characteristics into Specifications section. ................................................................................................. 15

Changes from Revision M (July 2012) to Revision N Page

• Updated document formatting ................................................................................................................................................ 1

• Removed Ordering Information table. .................................................................................................................................... 4
• Added Application Note links................................................................................................................................................ 22

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5 Device Comparison Table

DEVICE PINOUT INITIAL ACCURACY OPERATING FREE-AIR TEMPERATURE (TA)

B: 0.5% C: 0°C to 70°C
TL431
A: 1% I: -40°C to 85°C
TL432
(Blank): 2% Q: -40°C to 125°C

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6 Pin Configuration and Functions

TL431, TL431A, TL431B . . . LP (TO-92/TO-226) PACKAGE TL431 . . . KTP (PowerFLEX /TO-252) PACKAGE TL431A, TL431B . . . DCK (SC-70) PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW)

CATHODE CATHODE 1 6 ANODE

ANODE
CATHODE
NC 2 5 NC
ANODE
ANODE REF 3 4 NC
REF
REF NC − No internal connection

TL431, TL431A, TL431B . . . D (SOIC) PACKAGE TL431, TL431A, TL431B . . . P (PDIP), PS (SOP),
(TOP VIEW) OR PW (TSSOP) PACKAGE
(TOP VIEW)
CATHODE 1 8 REF
ANODE 2 7 ANODE CATHODE 1 8 REF
ANODE 3 6 ANODE NC 2 7 NC
NC 4 5 NC NC 3 6 ANODE
NC 4 5 NC
NC − No internal connection
NC − No internal connection

TL431, TL431A, TL431B . . . PK (SOT-89) PACKAGE TL432, TL432A, TL432B . . . PK (SOT-89) PACKAGE
(TOP VIEW) (TOP VIEW)

CATHODE REF
ANODE

ANODE
ANODE ANODE

REF CATHODE

TL432, TL432A, TL432B . . . DBV (SOT-23-5) PACKAGE

TL431, TL431A, TL431B . . . DBV (SOT-23-5) PACKAGE
(TOP VIEW)
(TOP VIEW)
NC 1 5 REF
NC 1 ANODE
5
ANODE 2
† 2
NC 3 4 CATHODE
CATHODE 3 4 REF

NC − No internal connection NC − No internal connection

† Pin 2 is attached to Substrate and must be
connected to ANODE or left open.

TL431, TL431A, TL431B . . . DBZ (SOT-23-3) PACKAGE TL432, TL432A, TL432B . . . DBZ (SOT-23-3) PACKAGE
(TOP VIEW) (TOP VIEW)

CATHODE 1 REF 1
3 ANODE 3 ANODE
REF 2 CATHODE 2

Pin Functions
PIN
TLV431x TLV432x
TYPE DESCRIPTION
NAME P, PS
DBZ DBV PK D LP KTP DCK DBZ DBV PK
PW
CATHODE 1 3 3 1 1 1 1 1 2 4 1 I/O Shunt Current/Voltage input
REF 2 4 1 8 8 3 3 3 1 5 3 I Threshold relative to common anode
2, 3,
ANODE 3 5 2 6 2 2 6 3 2 2 O Common pin, normally connected to ground
6, 7

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VKA Cathode voltage (2) 37 V
IKA Continuous cathode current range –100 150 mA
II(ref) Reference input current range –0.05 10 mA
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ANODE, unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±1000 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

7.3 Thermal Information

TL43xx
THERMAL METRIC (1) P PW D PS DCK DBV DBZ LP PK UNIT
8 PINS 6 PINS 5 PINS 3 PINS
RθJA Junction-to-ambient thermal
85 149 97 95 259 206 206 140 52
resistance
°C/W
RθJC(top) Junction-to-case (top) thermal
57 65 39 46 87 131 76 55 9
resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

7.4 Recommended Operating Conditions

See (1)
MIN MAX UNIT
VKA Cathode voltage Vref 36 V
IKA Cathode current 1 100 mA
TL43xxC 0 70
TA Operating free-air temperature TL43xxI –40 85 °C
TL43xxQ –40 125

(1) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.

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7.5 Electrical Characteristics, TL431C, TL432C

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431C, TL432C
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2440 2495 2550 mV
Deviation of reference input SOT23-3 and TL432
VKA = Vref, 6 16
VI(dev) voltage over full temperature See Figure 20 devices mV
IKA = 10 mA,
range (1) All other devices 4 25
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.4 1.2 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 1 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 1 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.6 Electrical Characteristics, TL431I, TL432I

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431I, TL432I
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2440 2495 2550 mV
Deviation of reference input SOT23-3 and TL432
VKA = Vref, 14 34
VI(dev) voltage over full temperature See Figure 20 devices mV
IKA = 10 mA
range (1) All other devices 5 50
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 2.5 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 1 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 1 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.7 Electrical Characteristics, TL431Q, TL432Q

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431Q, TL432Q
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2440 2495 2550 mV
Deviation of reference input
VI(dev) voltage over full temperature See Figure 20 VKA = Vref, IKA = 10 mA 14 34 mV
range (1)
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 2.5 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 1 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 1 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.8 Electrical Characteristics, TL431AC, TL432AC

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431AC, TL432AC
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2470 2495 2520 mV
Deviation of reference input SOT23-3 and TL432
VKA = Vref, 6 16
VI(dev) voltage over full temperature See Figure 20 devices mV
IKA = 10 mA
range (1) All other devices 4 25
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 1.2 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 0.6 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 0.5 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.9 Electrical Characteristics, TL431AI, TL432AI

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431AI, TL432AI
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2470 2495 2520 mV
Deviation of reference input SOT23-3 and TL432
VKA = Vref, 14 34
VI(dev) voltage over full temperature See Figure 20 devices mV
IKA = 10 mA
range (1) All other devices 5 50
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 2.5 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 0.7 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 0.5 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.10 Electrical Characteristics, TL431AQ, TL432AQ

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431AQ, TL432AQ
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2470 2495 2520 mV
Deviation of reference input
VI(dev) voltage over full temperature See Figure 20 VKA = Vref, IKA = 10 mA 14 34 mV
range (1)
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 2.5 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 0.7 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 0.5 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.11 Electrical Characteristics, TL431BC, TL432BC

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431BC, TL432BC
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2483 2495 2507 mV
Deviation of reference input
VI(dev) voltage over full temperature See Figure 20 VKA = Vref, IKA = 10 mA 6 16 mV
range (1)
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V – –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 1.2 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 0.6 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 0.5 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.12 Electrical Characteristics, TL431BI, TL432BI

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431BI, TL432BI
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2483 2495 2507 mV
Deviation of reference input
VI(dev) voltage over full temperature See Figure 20 VKA = Vref, IKA = 10 mA 14 34 mV
range (1)
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 2.5 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 0.7 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 0.5 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.13 Electrical Characteristics, TL431BQ, TL432BQ

over recommended operating conditions, TA = 25°C (unless otherwise noted)
TL431BQ, TL432BQ
PARAMETER TEST CIRCUIT TEST CONDITIONS UNIT
MIN TYP MAX
Vref Reference voltage See Figure 20 VKA = Vref, IKA = 10 mA 2483 2495 2507 mV
Deviation of reference input
VI(dev) voltage over full temperature See Figure 20 VKA = Vref, IKA = 10 mA 14 34 mV
range (1)
Ratio of change in reference ΔVKA = 10 V – Vref –1.4 –2.7
ΔVref /
voltage to the change in See Figure 21 IKA = 10 mA mV/V
ΔVKA ΔVKA = 36 V – 10 V –1 –2
cathode voltage
Iref Reference input current See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 2 4 µA
Deviation of reference input
II(dev) current over full temperature See Figure 21 IKA = 10 mA, R1 = 10 kΩ, R2 = ∞ 0.8 2.5 µA
range (1)
Minimum cathode current for
Imin See Figure 20 VKA = Vref 0.4 0.7 mA
regulation
Ioff Off-state cathode current See Figure 22 VKA = 36 V, Vref = 0 0.1 0.5 µA
(2)
|zKA| Dynamic impedance See Figure 20 VKA = Vref, f ≤ 1 kHz, IKA = 1 mA to 100 mA 0.2 0.5 Ω

(1) The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over
the rated temperature range. The average full-range temperature coefficient of the reference input voltage αVref is defined as:

αVref is positive or negative, depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature.
∆VKA
|zKA| =
(2) The dynamic impedance is defined as: ∆IKA
|z'| = ∆V
When the device is operating with two external resistors (see Figure 21), the total dynamic impedance of the circuit is given by: ∆I

which is approximately equal to ( (

|zKA| 1 + R1
R2 .

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7.14 Typical Characteristics

Data at high and low temperatures are applicable only within the recommended operating free-air temperature
ranges of the various devices.

2600 5
VKA = Vref R1 = 10 kΩ
2580 IKA = 10 mA R2 =∞
Vref = 2550 mV IKA = 10 mA
2560 4
V ref − Reference Voltage − mV

I ref − Reference Current − µA

2540

2520 3

Vref = 2495 mV
2500

2480 2

2460

2440 Vref = 2440 mV 1

2420

2400 0
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 1. Reference Voltage vs Free-Air Temperature Figure 2. Reference Current vs Free-Air Temperature
150 800
VKA = Vref VKA = Vref
125 TA = 25°C TA = 25°C

100 600
I KA − Cathode Current − µ A
I KA − Cathode Current − mA

75 Imin

50 400

25

0 200

−25

−50 0

−75

−100 −200
−2 −1 0 1 2 3 −1 0 1 2 3
VKA − Cathode Voltage − V VKA − Cathode Voltage − V
Figure 3. Cathode Current vs Cathode Voltage Figure 4. Cathode Current vs Cathode Voltage
2.5 − 0.85
VKA = 36 V
VKA = 3 V to 36 V
Vref = 0
− 0.95
I off − Off-State Cathode Current − µA

2
∆V ref / ∆V KA − mV/V

−1.05
1.5

−1.15

1
−1.25

0.5
−1.35
16 16

0 −1.45
−75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 5. Off-State Cathode Current Figure 6. Ratio of Delta Reference Voltage to Delta Cathode
vs Free-Air Temperature Voltage vs Free-Air Temperature

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Typical Characteristics (continued)

260 6
IO = 10 mA
Hz

V n − Equivalent Input Noise V oltage − µV

240 TA = 25°C
4
Vn − Equivalent Input Noise V oltage − nV/

220 3
2
200
1

180 0
−1
160
−2
140 −3

−4 f = 0.1 to 10 Hz
120
16 IKA = 10 mA
−5
TA = 25°C
100 −6
10 100 1k 10 k 100 k 0 1 2 3 4 5 6 7 8 9 10
f − Frequency − Hz t − Time − s
Figure 7. Equivalent Input Noise Voltage vs Frequency Figure 8. Equivalent Input Noise Voltage Over a 10-S Period
19.1 V

1 kΩ

500 µF 910 Ω
2000 µF
VCC VCC
1 µF
TL431
(DUT) TLE2027
AV = 10 V/mV
+ 22 µF
820 Ω + TLE2027 To
− 16 kΩ 16 kΩ Oscilloscope
16 Ω −
160 kΩ 1 µF 33 kΩ

0.1 µF AV = 2 V/V
33 kΩ

VEE VEE

Figure 9. Test Circuit for Equivalent Input Noise Voltage Over a 10-S Period

60 IKA = 10 mA
IKA = 10 mA TA = 25°C
A V − Small-Signal V oltage Amplification − dB

TA = 25°C
50

40
Output
IKA
15 kΩ 232 Ω
30

9 µF
20 +

−
10 8.25 kΩ

0 GND
1k 10 k 100 k 1M 10 M
f − Frequency − Hz
Figure 10. Small-Signal Voltage Amplification Figure 11. Test Circuit for Voltage Amplification
vs Frequency

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Typical Characteristics (continued)

100 1 kΩ
IKA = 10 mA Output
TA = 25°C
|z KA| − Reference Impedance − Ω

IKA
10 50 Ω
−

+
GND
1

0.1
1k 10 k 100 k 1M 10 M
f − Frequency − Hz
Figure 12. Reference Impedance vs Frequency Figure 13. Test Circuit for Reference Impedance
6 220 Ω
TA = 25°C
Output
Input
5
Input and Output V oltage − V

Pulse
4 50 Ω
Generator
f = 100 kHz
3
Output

2 GND

0
−1 0 1 2 3 4 5 6 7
t − Time − µs
Figure 14. Pulse Response Figure 15. Test Circuit for Pulse Response
100 150 Ω
A V KA = Vref TA = 25°C
90 B V KA =5V
C VKA = 10 V IKA
80 D VKA = 15 Vf
+
B VBATT
I KA − Cathode Current − mA

70 CL
−
Stable
60
Stable C
50
A
40
TEST CIRCUIT FOR CURVE A
30
D
20
IKA
10
R1 = 10 kΩ 150 Ω
0
0.001 0.01 0.1 1 10
CL
CL − Load Capacitance − µF
+
The areas under the curves represent conditions that may cause R2 VBATT
the device to oscillate. For curves B, C, and D, R2 and V+ are −
adjusted to establish the initial VKA and IKA conditions, with CL = 0.
VBATT and CL then are adjusted to determine the ranges of
stability.
TEST CIRCUIT FOR CURVES B, C, AND D

Figure 16. Stability Boundary Conditions for All TL431 and Figure 17. Test Circuits for Stability Boundary Conditions
TL431A Devices
(Except for SOT23-3, SC-70, and Q-Temp Devices)

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Typical Characteristics (continued)

100 150 Ω
A VKA = Vref
90 B V KA =5V
C VKA = 10 V IKA
80 D VKA = 15 Vf +
B CL VBATT
I KA − Cathode Current − mA

70 −
TA = 25°C
60
Stable C
Stable
50
A
40 TEST CIRCUIT FOR CURVE A
A
30
D
IKA
20
R1 = 10 kΩ 150 Ω
B
10
CL
0
+
0.001 0.01 0.1 1 10
R2 VBATT
CL − Load Capacitance − µF −
The areas under the curves represent conditions that may cause
the device to oscillate. For curves B, C, and D, R2 and V+ are
adjusted to establish the initial VKA and IKA conditions, with CL = 0.
TEST CIRCUIT FOR CURVES B, C, AND D
VBATT and CL then are adjusted to determine the ranges of
stability.

Figure 18. Stability Boundary Conditions for All TL431B, Figure 19. Test Circuit for Stability Boundary Conditions
TL432, SOT-23, SC-70, and Q-Temp Devices

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8 Parameter Measurement Information

Input VKA
IKA

Vref

Figure 20. Test Circuit for VKA = Vref

Input VKA

IKA

R1 Iref

R2 Vref æ R1 ö
VKA = Vref ç 1 + ÷ + Iref × R1
è R2 ø

Figure 21. Test Circuit for VKA > Vref

Input VKA
Ioff

Figure 22. Test Circuit for Ioff

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9 Detailed Description

9.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications, ranging from power
to signal path. This is due to it's key components containing an accurate voltage reference & opamp, which are
very fundamental analog building blocks. TL43xx is used in conjunction with it's key components to behave as a
single voltage reference, error amplifier, voltage clamp or comparator with integrated reference.
TL43xx can be operated and adjusted to cathode voltages from 2.5V to 36V, making this part optimum for a wide
range of end equipments in industrial, auto, telecom & computing. In order for this device to behave as a shunt
regulator or error amplifier, >1mA (Imin(max)) must be supplied in to the cathode pin. Under this condition,
feedback can be applied from the Cathode and Ref pins to create a replica of the internal reference voltage.
Various reference voltage options can be purchased with initial tolerances (at 25°C) of 0.5%, 1%, and 2%. These
reference options are denoted by B (0.5%), A (1.0%) and blank (2.0%) after the TL431 or TL432. TL431 & TL432
are both functionaly, but have separate pinout options.
The TL43xxC devices are characterized for operation from 0°C to 70°C, the TL43xxI devices are characterized
for operation from –40°C to 85°C, and the TL43xxQ devices are characterized for operation from –40°C to
125°C.

9.2 Functional Block Diagram

CATHODE

REF +
_

Vref

ANODE

Figure 23. Equivalent Schematic

CATHODE
800 Ω 800 Ω

20 pF
REF

150 Ω

3.28 kΩ 4 kΩ 10 kΩ

2.4 kΩ 7.2 kΩ 20 pF

1 kΩ

800 Ω
ANODE

Figure 24. Detailed Schematic

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9.3 Feature Description

TL43xx consists of an internal reference and amplifier that outputs a sink current base on the difference between
the reference pin and the virtual internal pin. The sink current is produced by the internal Darlington pair, shown
in the above schematic (Figure 24). A Darlington pair is used in order for this device to be able to sink a
maximum current of 100 mA.
When operated with enough voltage headroom (≥ 2.5 V) and cathode current (IKA), TL431 forces the reference
pin to 2.5 V. However, the reference pin can not be left floating, as it needs IREF ≥ 4 µA (please see Electrical
Characteristics, TL431C, TL432C). This is because the reference pin is driven into an npn, which needs base
current in order operate properly.
When feedback is applied from the Cathode and Reference pins, TL43xx behaves as a Zener diode, regulating
to a constant voltage dependent on current being supplied into the cathode. This is due to the internal amplifier
and reference entering the proper operating regions. The same amount of current needed in the above feedback
situation must be applied to this device in open loop, servo or error amplifying implementations in order for it to
be in the proper linear region giving TL43xx enough gain.
Unlike many linear regulators, TL43xx is internally compensated to be stable without an output capacitor
between the cathode and anode. However, if it is desired to use an output capacitor Figure 24 can be used as a
guide to assist in choosing the correct capacitor to maintain stability.

9.4 Device Functional Modes

9.4.1 Open Loop (Comparator)
When the cathode/output voltage or current of TL43xx is not being fed back to the reference/input pin in any
form, this device is operating in open loop. With proper cathode current (Ika) applied to this device, TL43xx will
have the characteristics shown in Figure 23. With such high gain in this configuration, TL43xx is typically used as
a comparator. With the reference integrated makes TL43xx the prefered choice when users are trying to monitor
a certain level of a single signal.

9.4.2 Closed Loop

When the cathode/output voltage or current of TL43xx is being fed back to the reference/input pin in any form,
this device is operating in closed loop. The majority of applications involving TL43xx use it in this manner to
regulate a fixed voltage or current. The feedback enables this device to behave as an error amplifier, computing
a portion of the output voltage and adjusting it to maintain the desired regulation. This is done by relating the
output voltage back to the reference pin in a manner to make it equal to the internal reference voltage, which can
be accomplished via resistive or direct feedback.

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10 Applications and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

As this device has many applications and setups, there are many situations that this datasheet can not
characterize in detail. The linked application notes will help the designer make the best choices when using this
part.
Application note Understanding Stability Boundary Conditions Charts in TL431, TL432 Data Sheet (SLVA482)
will provide a deeper understanding of this devices stability characteristics and aid the user in making the right
choices when choosing a load capacitor. Application note Setting the Shunt Voltage on an Adjustable Shunt
Regulator (SLVA445) assists designers in setting the shunt voltage to achieve optimum accuracy for this device.

10.2 Typical Applications

10.2.1 Comparator With Integrated Reference
Vsup

Rsup
Vout

CATHODE
R1
VL
RIN
VIN REF
+

R2
2.5V

ANODE

Figure 25. Comparator Application Schematic

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Typical Applications (continued)

10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input Voltage Range 0 V to 5 V
Input Resistance 10 kΩ
Supply Voltage 24 V
Cathode Current (Ik) 5 mA
Output Voltage Level ~2 V – VSUP
Logic Input Thresholds VIH/VIL VL

10.2.1.2 Detailed Design Procedure

When using TL431 as a comparator with reference, determine the following:
• Input Voltage Range
• Reference Voltage Accuracy
• Output logic input high and low level thresholds
• Current Source resistance

10.2.1.2.1 Basic Operation

In the configuration shown in Figure 25 TL431 will behave as a comparator, comparing the VREF pin voltage to
the internal virtual reference voltage. When provided a proper cathode current (IK), TL43xx will have enough
open loop gain to provide a quick response. This can be seen in Figure 26, where the RSUP=10 kΩ (IKA=500 µA)
situation responds much slower than RSUP=1 kΩ (IKA=5 mA). With the TL43xx's max Operating Current (IMIN)
being 1 mA, operation below that could result in low gain, leading to a slow response.

10.2.1.2.1.1 Overdrive
Slow or inaccurate responses can also occur when the reference pin is not provided enough overdrive voltage.
This is the amount of voltage that is higher than the internal virtual reference. The internal virtual reference
voltage will be within the range of 2.5 V ±(0.5%, 1.0% or 1.5%) depending on which version is being used. The
more overdrive voltage provided, the faster the TL431 will respond.
For applications where TL431 is being used as a comparator, it is best to set the trip point to greater than the
positive expected error (i.e. +1.0% for the A version). For fast response, setting the trip point to >10% of the
internal VREF should suffice.
For minimal voltage drop or difference from Vin to the ref pin, it is recommended to use an input resistor <10kΩ
to provide Iref.

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10.2.1.2.2 Output Voltage and Logic Input Level

In order for TL431 to properly be used as a comparator, the logic output must be readable by the receiving logic
device. This is accomplished by knowing the input high and low level threshold voltage levels, typically denoted
by VIH & VIL.
As seen in Figure 26, TL431's output low level voltage in open-loop/comparator mode is ~2 V, which is typically
sufficient for 5V supplied logic. However, would not work for 3.3 V & 1.8 V supplied logic. In order to accomodate
this a resistive divider can be tied to the output to attenuate the output voltage to a voltage legible to the
receiving low voltage logic device.
TL431's output high voltage is equal to VSUP due to TL431 being open-collector. If VSUP is much higher than the
receiving logic's maximum input voltage tolerance, the output must be attenuated to accomadate the outgoing
logic's reliability.
When using a resistive divider on the output, be sure to make the sum of the resistive divider (R1 & R2 in
Figure 25) is much greater than RSUP in order to not interfere with TL431's ability to pull close to VSUP when
turning off.

10.2.1.2.2.1 Input Resistance

TL431 requires an input resistance in this application in order to source the reference current (IREF) needed from
this device to be in the proper operating regions while turing on. The actual voltage seen at the ref pin will be
VREF=VIN-IREF*RIN. Since IREF can be as high as 4 µA it is recommended to use a resistance small enough that
will mitigate the error that IREF creates from VIN.

10.2.1.3 Application Curve

5.5
5
4.5
4
3.5
Voltage (V)

3
2.5
2
1.5
1
Vin
0.5 Vka(Rsup=10k:)
0 Vka(Rsup=1k:)
-0.5
-0.001 -0.0006 -0.0002 0.0002 0.0006 0.001
Time (s) D001

Figure 26. Output Response With Various Cathode Currents

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10.2.2 Shunt Regulator/Reference

RSUP R1
VSUP VO = ( 1 + ) Vref
R2
R1
CATHODE
0.1%
REF
Vr ef TL431
ANODE
CL
R2
0.1%

Figure 27. Shunt Regulator Schematic

10.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Reference Initial Accuracy 1.0 %
Supply Voltage 24 V
Cathode Current (Ik) 5 mA
Output Voltage Level 2.5 V - 36 V
Load Capacitance 100 nF
Feedback Resistor Values and Accuracy (R1 & R2) 10 kΩ

10.2.2.2 Detailed Design Procedure

When using TL431 as a Shunt Regulator, determine the following:
• Input Voltage Range
• Temperature Range
• Total Accuracy
• Cathode Current
• Reference Initial Accuracy
• Output Capacitance

10.2.2.2.1 Programming Output/Cathode Voltage

In order to program the cathode voltage to a regulated voltage a resistive bridge must be shunted between the
cathode and anode pins with the mid point tied to the reference pin. This can be seen in Figure 27, with R1 & R2
being the resistive bridge. The cathode/output voltage in the shunt regulator configuration can be approximated
by the equation shown in Figure 27. The cathode voltage can be more accuratel determined by taking in to
account the cathode current:
Vo=(1+R1/R2)*VREF-IREF*R1
In order for this equation to be valid, TL43xx must be fully biased so that it has enough open loop gain to mitigate
any gain error. This can be done by meeting the Imin spec denoted in Electrical Characteristics, TL431C,
TL432C.

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10.2.2.2.2 Total Accuracy

When programming the output above unity gain (VKA=VREF), TL43xx is susceptible to other errors that may effect
the overall accuracy beyond VREF. These errors include:
• R1 and R2 accuracies
• VI(dev) - Change in reference voltage over temperature
• ΔVREF / ΔVKA - Change in reference voltage to the change in cathode voltage
• |zKA| - Dynamic impedance, causing a change in cathode voltage with cathode current
Worst case cathode voltage can be determined taking all of the variables in to account. Application note Setting
the Shunt Voltage on an Adjustable Shunt Regulator (SLVA445) assists designers in setting the shunt voltage to
achieve optimum accuracy for this device.

10.2.2.2.3 Stability
Though TL43xx is stable with no capacitive load, the device that receives the shunt regulator's output voltage
could present a capacitive load that is within the TL43xx region of stability, shown inFigure 16 and Figure 18.
Also, designers may use capacitive loads to improve the transient response or for power supply decoupling.
When using additional capacitance between Cathode and Anode, refer to Figure 16 and Figure 18. Also,
application note Understanding Stability Boundary Conditions Charts in TL431, TL432 Data Sheet (SLVA482) will
provide a deeper understanding of this devices stability characteristics and aid the user in making the right
choices when choosing a load capacitor.

10.2.2.2.4 Start-Up Time

As shown in Figure 28, TL43xx has a fast response up to ~2 V and then slowly charges to it's programmed
value. This is due to the compensation capacitance (shown in Figure 24) the TL43xx has to meet it's stability
criteria. Despite the secondary delay, TL43xx still has a fast response suitable for many clamp applications.

10.2.2.3 Application Curve

27
Vsup
24
Vka=Vref
21 R1=10k: & R2=10k:
R1=38k: & R2=10k:
18
15
Voltage (V)

12
9
6
3
0
-3
-6
-5E-6 -3E-6 -1E-6 1E-6 3E-6 5E-6
Time (s) D001

Figure 28. TL43xx Start-Up Response

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10.3 System Examples

VI(BATT)
R
(see Note A) 2N222

2N222
30 Ω

0.01 µF 4.7 kΩ
TL431 VO
R1
R2 æ R1 ö
0.1% VO = ç 1 +
0.1% ÷ Vref
è R2 ø

A. R should provide cathode current ≥1 mA to the TL431 at minimum V(BATT).

Figure 29. Precision High-Current Series Regulator

VI(BATT)
IN
OUT
uA7805 VO

Common R1
(
VO = 1 + R1 Vref (
R2
TL431 Minimum V V + 5V
O = ref
R2

Figure 30. Output Control of a Three-Terminal Fixed Regulator

VI(BATT) VO

R1 (
VO = 1 + R1 Vref(
R2

R2 TL431

Figure 31. High-Current Shunt Regulator

VI(BATT) VO

R1

TL431

C
(see Note A)
R2

A. Refer to the stability boundary conditions in Figure 16 and Figure 18 to determine allowable values for C.

Figure 32. Crowbar Circuit

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System Examples (continued)

IN OUT
VI(BATT) LM317 VO ≈5 V, 1.5 A

8.2 kΩ Adjust
243 Ω
0.1%

TL431
243 Ω
0.1%

Figure 33. Precision 5-V, 1.5-A Regulator

VI(BATT) VO ≈5 V
Rb
(see Note A) 27.4 kΩ
0.1%

TL431
27.4 kΩ
0.1%

A. Rb should provide cathode current ≥1 mA to the TL431.

Figure 34. Efficient 5-V Precision Regulator

12 V

VCC
6.8 kΩ

5V 10 kΩ
−
10 kΩ
+
0.1% TL598
X
TL431 Not
10 kΩ Used
0.1%

Feedback

Figure 35. PWM Converter With Reference

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System Examples (continued)

R3
(see Note A)
VI(BATT)
R4
R1A R1B
(see Note A)
Low Limit = 1 + R1B V ref
R2B
TL431
High Limit = 1 + R1A V ref
R2A
LED on When Low Limit < VI(BATT) < High Limit
R2A R2B

A. Select R3 and R4 to provide the desired LED intensity and cathode current ≥1 mA to the TL431 at the available
VI(BATT).

Figure 36. Voltage Monitor

650 Ω
12 V

R 2 kΩ

TL431

C æ 12 V ö
On Delay = R × C × In çç
Off 12 V – V ÷÷
è ref ø

Figure 37. Delay Timer

RCL IO
0.1% V ref
VI(BATT) Iout = + IKA
R CL

R1 V I(BATT)
TL431 R1 = I
O
h FE + IKA

Figure 38. Precision Current Limiter

Copyright © 2004–2018, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: TL431 TL432
TL431, TL432
SLVS543P – AUGUST 2004 – REVISED NOVEMBER 2018 www.ti.com

System Examples (continued)

VI(BATT)
IO

Vref
IO =
RS
TL431
RS
0.1%

Figure 39. Precision Constant-Current Sink

11 Power Supply Recommendations

When using TL43xx as a Linear Regulator to supply a load, designers will typically use a bypass capacitor on the
output/cathode pin. When doing this, be sure that the capacitance is within the stability criteria shown in
Figure 16 and Figure 18.
In order to not exceed the maximum cathode current, be sure that the supply voltage is current limited. Also, be
sure to limit the current being driven into the Ref pin, as not to exceed it's absolute maximum rating.
For applications shunting high currents, pay attention to the cathode and anode trace lengths, adjusting the width
of the traces to have the proper current density.

12 Layout

12.1 Layout Guidelines

Bypass capacitors should be placed as close to the part as possible. Current-carrying traces need to have widths
appropriate for the amount of current they are carrying; in the case of the TL43xx, these currents will be low.

12.2 Layout Example

TL432 - DBZ
(TOP VIEW)
Rref
REF
Vin 1 ANODE
Rsup CATHODE 3
GND
Vsup 2

CL

GND

Figure 40. DBZ Layout Example

30 Submit Documentation Feedback Copyright © 2004–2018, Texas Instruments Incorporated

Product Folder Links: TL431 TL432

 TL431, TL432
www.ti.com SLVS543P – AUGUST 2004 – REVISED NOVEMBER 2018

13 Device and Documentation Support

13.1 Device Nomenclature

TI assigns suffixes and prefixes to differentiate all the combinations of the TL43x family. The Eco Plan designator
is a legacy designator that was used to differentiate Pb-free and Green devices. More details and possible
orderable combinations are located on the Package Option Addendum in Mechanical, Packaging, and Orderable
Information.

TL431 X X XXX X XX

Initial Operating Free-Air Package Package

Product Accuracy Temperature Type Quantity Eco Plan
1: TL431 B: 0.5% C: 0°C to 70°C LP: TO-92 R: Tape & Reel G3: Legacy Designator
2: TL432* A: 1% I: -40°C to 85°C LPM: TO-92 T: Small Tape & Reel G4: Legacy Designator
*(Cathode and REF (Blank): 2% Q: -40°C to 125°C (Formed Lead) E3: Legacy Designator
pins are switched) DCK: SC-70 E4: Legacy Designator
D: SOIC
P: PDIP
PK: SOT-89
PS: SO
DBV: SOT-23-5
DBZ: SOT-23-3
PW: TSSOP

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TL431 Click here Click here Click here Click here Click here
TL432 Click here Click here Click here Click here Click here

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

13.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2004–2018, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TL431 TL432
TL431, TL432
SLVS543P – AUGUST 2004 – REVISED NOVEMBER 2018 www.ti.com

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

32 Submit Documentation Feedback Copyright © 2004–2018, Texas Instruments Incorporated

Product Folder Links: TL431 TL432

 PACKAGE OPTION ADDENDUM

www.ti.com 30-May-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431ACD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 431AC

& no Sb/Br)
TL431ACDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (TACG, TACS)
& no Sb/Br)
TL431ACDBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TACG
& no Sb/Br)
TL431ACDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TACG
& no Sb/Br)
TL431ACDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (TACG, TACU)
& no Sb/Br)
TL431ACDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (TAC3, TACG, TACS,
& no Sb/Br) TACU)
TL431ACDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TAC3
& no Sb/Br)
TL431ACDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (TAC3, TACG, TACS,
& no Sb/Br) TACU)
TL431ACDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TAC3
& no Sb/Br)
TL431ACDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 (T4S, T4U)
& no Sb/Br)
TL431ACDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 431AC
& no Sb/Br)
TL431ACDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 431AC
& no Sb/Br)
TL431ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 431AC
& no Sb/Br)
TL431ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 431AC
& no Sb/Br)
TL431ACLP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431AC
(RoHS)
TL431ACLPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431AC
(RoHS)
TL431ACLPM ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431AC
(RoHS)

Addendum-Page 1
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431ACLPME3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431AC

(RoHS)
TL431ACLPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431AC
(RoHS)
TL431ACLPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431AC
(RoHS)
TL431ACP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TL431ACP
& no Sb/Br)
TL431ACPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 4A
& no Sb/Br)
TL431ACPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 4A
& no Sb/Br)
TL431ACPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431A
& no Sb/Br)
TL431ACPW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431A
& no Sb/Br)
TL431ACPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431A
& no Sb/Br)
TL431AID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (TAIG, TAIS)
& no Sb/Br)
TL431AIDBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TAIG
& no Sb/Br)
TL431AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TAIG
& no Sb/Br)
TL431AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (TAIG, TAIU)
& no Sb/Br)
TL431AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TAIG
& no Sb/Br)
TL431AIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T3AG, TAI3, TAIS,
& no Sb/Br) TAIU)
TL431AIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TAI3
& no Sb/Br)
TL431AIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T3AG, TAI3, TAIS,
& no Sb/Br) TAIU)

Addendum-Page 2
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431AIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TAI3
& no Sb/Br)
TL431AIDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T5U
& no Sb/Br)
TL431AIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 431AI
& no Sb/Br)
TL431AILP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPM ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPME3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431AI
(RoHS)
TL431AIP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431AIP
& no Sb/Br)
TL431AIPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431AIP
& no Sb/Br)
TL431AIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4B
& no Sb/Br)
TL431AIPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4B
& no Sb/Br)

Addendum-Page 3
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431AQDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (TAQG, TAQU)
& no Sb/Br)
TL431AQDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (TAQG, TAQU)
& no Sb/Br)
TL431AQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (TAQ3, TAQG, TAQS,
& no Sb/Br) TAQU)
TL431AQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TAQS
& no Sb/Br)
TL431AQDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (TAQG, TAQS, TAQU)
& no Sb/Br)
TL431AQDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TAQS
& no Sb/Br)
TL431AQDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T7U
& no Sb/Br)
TL431AQDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T7U
& no Sb/Br)
TL431AQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 4D
& no Sb/Br)
TL431AQPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 4D
& no Sb/Br)
TL431BCD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3GG, T3GU)
& no Sb/Br)
TL431BCDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3GG, T3GU)
& no Sb/Br)
TL431BCDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3GG
& no Sb/Br)
TL431BCDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T3G3, T3GG, T3GS,
& no Sb/Br) T3GU)
TL431BCDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3G3
& no Sb/Br)
TL431BCDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T3G3, T3GG, T3GS,
& no Sb/Br) T3GU)
TL431BCDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3G3
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431BCDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T2U
& no Sb/Br)
TL431BCDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T2U
& no Sb/Br)
TL431BCDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCLP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 T431B
(RoHS)
TL431BCLPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 T431B
(RoHS)
TL431BCLPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 T431B
(RoHS)
TL431BCP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TL431BCP
& no Sb/Br)
TL431BCPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 4C
& no Sb/Br)
TL431BCPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 4C
& no Sb/Br)
TL431BCPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BCPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431B
& no Sb/Br)
TL431BID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3FG, T3FU)
& no Sb/Br)
TL431BIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3FG, T3FU)
& no Sb/Br)
TL431BIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3FG
& no Sb/Br)
TL431BIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T3F3, T3FG, T3FS,
& no Sb/Br) T3FU)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431BIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3F3
& no Sb/Br)
TL431BIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T3F3, T3FG, T3FS,
& no Sb/Br) T3FU)
TL431BIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3F3
& no Sb/Br)
TL431BIDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3U
& no Sb/Br)
TL431BIDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z431B
& no Sb/Br)
TL431BILP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BILPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 Z431B
(RoHS)
TL431BIP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431BIP
& no Sb/Br)
TL431BIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4I
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431BIPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 4I

& no Sb/Br)
TL431BQD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431BQ
& no Sb/Br)
TL431BQDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 T3HU
& no Sb/Br)
TL431BQDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3HU
& no Sb/Br)
TL431BQDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 T3HU
& no Sb/Br)
TL431BQDBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 T3HU
& no Sb/Br)
TL431BQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T3H3, T3HG, T3HS,
& no Sb/Br) T3HU)
TL431BQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3HS
& no Sb/Br)
TL431BQDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T3HG, T3HS, T3HU)
& no Sb/Br)
TL431BQDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3HS
& no Sb/Br)
TL431BQDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T8U
& no Sb/Br)
TL431BQDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T8U
& no Sb/Br)
TL431BQDCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T8U
& no Sb/Br)
TL431BQDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431BQ
& no Sb/Br)
TL431BQDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431BQ
& no Sb/Br)
TL431BQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431BQ
& no Sb/Br)
TL431BQLP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQLPM ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431BQLPME3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQLPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQLPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 125 T431BQ
(RoHS)
TL431BQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3H
& no Sb/Br)
TL431BQPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3H
& no Sb/Br)
TL431BQPSR PREVIEW SO PS 8 2000 TBD Call TI Call TI -40 to 125
TL431CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL431C
& no Sb/Br)
TL431CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3CG, T3CS)
& no Sb/Br)
TL431CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T3CG, T3CS)
& no Sb/Br)
TL431CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3CG
& no Sb/Br)
TL431CDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T3C3, T3CG, T3CS,
& no Sb/Br) T3CU)
TL431CDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3C3
& no Sb/Br)
TL431CDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T3CG, T3CS, T3CU)
& no Sb/Br)
TL431CDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T3CS
& no Sb/Br)
TL431CDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL431C
& no Sb/Br)
TL431CDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL431C
& no Sb/Br)
TL431CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 TL431C
& no Sb/Br)
TL431CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL431C
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431CLP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431C

(RoHS)
TL431CLPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431C
(RoHS)
TL431CLPM ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431C
(RoHS)
TL431CLPME3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431C
(RoHS)
TL431CLPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431C
(RoHS)
TL431CLPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type 0 to 70 TL431C
(RoHS)
TL431CP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TL431CP
& no Sb/Br)
TL431CPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 TL431CP
& no Sb/Br)
TL431CPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 43
& no Sb/Br)
TL431CPKE6 ACTIVE SOT-89 PK 3 1000 Pb-Free CU SNBI Level-1-260C-UNLIM 0 to 70 43
(RoHS)
TL431CPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 43
& no Sb/Br)
TL431CPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431
& no Sb/Br)
TL431CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431
& no Sb/Br)
TL431CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T431
& no Sb/Br)
TL431ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3IG, T3IS)
& no Sb/Br)
TL431IDBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3IG
& no Sb/Br)
TL431IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3IG
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T3IG, T3IU)
& no Sb/Br)
TL431IDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T3I3, T3IG, T3IS,
& no Sb/Br) T3IU)
TL431IDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3IS
& no Sb/Br)
TL431IDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T3IG, T3IS, T3IU)
& no Sb/Br)
TL431IDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T3IS
& no Sb/Br)
TL431IDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL431I
& no Sb/Br)
TL431ILP ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431ILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431ILPR ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431ILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free CU SN N / A for Pkg Type -40 to 85 TL431I
(RoHS)
TL431IP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431IP
& no Sb/Br)
TL431IPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 TL431IP
& no Sb/Br)
TL431IPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 3I
& no Sb/Br)
TL431IPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 3I
& no Sb/Br)
TL431QD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431Q
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL431QDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (T3QG, T3QU)
& no Sb/Br)
TL431QDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3QG
& no Sb/Br)
TL431QDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (T3QG, T3QU)
& no Sb/Br)
TL431QDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T3Q3, T3QG, T3QS,
& no Sb/Br) T3QU)
TL431QDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3QS
& no Sb/Br)
TL431QDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T3QG, T3QS, T3QU)
& no Sb/Br)
TL431QDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T3QS
& no Sb/Br)
TL431QDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T6U
& no Sb/Br)
TL431QDCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T6U
& no Sb/Br)
TL431QDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T6U
& no Sb/Br)
TL431QDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T431Q
& no Sb/Br)
TL431QPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3Q
& no Sb/Br)
TL431QPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 3Q
& no Sb/Br)
TL432ACDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T4BG, T4BU)
& no Sb/Br)
TL432ACDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T4B3, T4BG, T4BS,
& no Sb/Br) T4BU)
TL432ACDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T4BS
& no Sb/Br)
TL432ACDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T4BG, T4BS, T4BU)
& no Sb/Br)
TL432ACDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T4BS
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL432AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T4AG, T4AU)
& no Sb/Br)
TL432AIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T4A3, T4AG, T4AS,
& no Sb/Br) T4AU)
TL432AIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T4A3
& no Sb/Br)
TL432AIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T4A3, T4AG, T4AS,
& no Sb/Br) T4AU)
TL432AIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T4A3
& no Sb/Br)
TL432AIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 2E
& no Sb/Br)
TL432AQDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 T4DU
& no Sb/Br)
TL432AQDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 T4DU
& no Sb/Br)
TL432AQDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4DU
& no Sb/Br)
TL432AQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T4D3, T4DG, T4DS,
& no Sb/Br) T4DU)
TL432AQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4DS
& no Sb/Br)
TL432AQDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T4DG, T4DS, T4DU)
& no Sb/Br)
TL432AQDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4DS
& no Sb/Br)
TL432AQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2F
& no Sb/Br)
TL432AQPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2F
& no Sb/Br)
TL432BCDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 TBCU
& no Sb/Br)
TL432BCDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (TBCG, TBCS, TBCU)
& no Sb/Br)
TL432BCDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TBCS
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL432BCDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (TBCG, TBCS, TBCU)
& no Sb/Br)
TL432BCDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TBCS
& no Sb/Br)
TL432BCPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 2G
& no Sb/Br)
TL432BIDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T4F3, T4FG, T4FS,
& no Sb/Br) T4FU)
TL432BIDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T4F3
& no Sb/Br)
TL432BIDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T4F3, T4FG, T4FS,
& no Sb/Br) T4FU)
TL432BIDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T4F3
& no Sb/Br)
TL432BIPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 2H
& no Sb/Br)
TL432BQDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4H3, T4HS, T4HU)
& no Sb/Br)
TL432BQDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (T4H3, T4HS, T4HU)
& no Sb/Br)
TL432BQPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2J
& no Sb/Br)
TL432CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 (T4CG, T4CU)
& no Sb/Br)
TL432CDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 (T4CG, T4CS, T4CU)
& no Sb/Br)
TL432CDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 T4CS
& no Sb/Br)
TL432CPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 2A
& no Sb/Br)
TL432IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (T4IG, T4IU)
& no Sb/Br)
TL432IDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T4IG, T4IS, T4IU)
& no Sb/Br)
TL432IDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T4IS
& no Sb/Br)

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL432IDBZT ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 (T4IG, T4IS, T4IU)
& no Sb/Br)
TL432IDBZTG4 ACTIVE SOT-23 DBZ 3 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 T4IS
& no Sb/Br)
TL432IPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 2B
& no Sb/Br)
TL432QDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 (T4QG, T4QS, T4QU)
& no Sb/Br)
TL432QDBZRG4 ACTIVE SOT-23 DBZ 3 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 T4QS
& no Sb/Br)
TL432QPK ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2C
& no Sb/Br)
TL432QPKG3 ACTIVE SOT-89 PK 3 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 2C
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

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 PACKAGE OPTION ADDENDUM

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(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 15
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL431ACDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431ACDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TL431ACDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431ACDBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431ACDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431ACDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431ACDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431ACDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431ACDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431ACDBZTG4 SOT-23 DBZ 3 250 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431ACDCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3
TL431ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431ACDR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
TL431ACDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431ACPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431ACPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL431AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431AIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

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 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL431AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431AIDBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431AIDBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431AIDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431AIDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431AIDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431AIDBZTG4 SOT-23 DBZ 3 250 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431AIDCKR SC70 DCK 6 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431AIDCKT SC70 DCK 6 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431AIDR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
TL431AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431AIDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431AIPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431AQDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431AQDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431AQDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431AQDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431AQDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431AQDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431AQDCKR SC70 DCK 6 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431AQDCKT SC70 DCK 6 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431AQPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431BCDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431BCDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431BCDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431BCDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431BCDBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431BCDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431BCDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431BCDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431BCDBZTG4 SOT-23 DBZ 3 250 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431BCDCKR SC70 DCK 6 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431BCDCKT SC70 DCK 6 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431BCPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431BCPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL431BIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431BIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431BIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431BIDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431BIDBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

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 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL431BIDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431BIDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431BIDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431BIDBZTG4 SOT-23 DBZ 3 250 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431BIDCKR SC70 DCK 6 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431BIDCKT SC70 DCK 6 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431BIDR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
TL431BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431BIDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431BIPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431BQDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL431BQDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL431BQDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431BQDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431BQDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431BQDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431BQDCKR SC70 DCK 6 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431BQDCKT SC70 DCK 6 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431BQDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431CDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TL431CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431CDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TL431CDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431CDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431CDBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431CDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431CDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL431CDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431CDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431CDR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
TL431CDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431CPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431CPKE6 SOT-89 PK 3 1000 180.0 13.0 4.91 4.52 1.9 8.0 12.0 Q3
TL431CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TL431IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TL431IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431IDBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL431IDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL431IDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431IDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431IDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431IDR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
TL431IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431IDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL431IPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL431QDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431QDBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431QDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL431QDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431QDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431QDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL431QDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL431QDCKR SC70 DCK 6 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431QDCKT SC70 DCK 6 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
TL431QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL432ACDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL432ACDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432ACDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432ACDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432ACDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL432AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL432AIDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432AIDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL432AIDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432AIDBZTG4 SOT-23 DBZ 3 250 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL432AIPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL432AQDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL432AQDBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL432AQDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432AQDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432AQDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432AQDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432AQPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL432BCDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL432BCDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TL432BCDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432BCDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432BCDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432BCDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432BCPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3

Pack Materials-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL432BIDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432BIDBZRG4 SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL432BIDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432BIDBZTG4 SOT-23 DBZ 3 250 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL432BIPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL432BQDBZR SOT-23 DBZ 3 3000 178.0 9.2 3.15 2.77 1.22 4.0 8.0 Q3
TL432BQDBZR SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432BQPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL432CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL432CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL432CDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432CDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432CPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL432IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TL432IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TL432IDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432IDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432IDBZT SOT-23 DBZ 3 250 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432IDBZTG4 SOT-23 DBZ 3 250 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432IPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3
TL432QDBZR SOT-23 DBZ 3 3000 178.0 9.0 3.15 2.77 1.22 4.0 8.0 Q3
TL432QDBZRG4 SOT-23 DBZ 3 3000 180.0 8.4 3.15 2.77 1.22 4.0 8.0 Q3
TL432QPK SOT-89 PK 3 1000 180.0 12.4 4.91 4.52 1.9 8.0 12.0 Q3

Pack Materials-Page 5
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431ACDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431ACDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431ACDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431ACDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431ACDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431ACDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431ACDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431ACDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431ACDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431ACDBZTG4 SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431ACDCKR SC70 DCK 6 3000 183.0 183.0 20.0
TL431ACDR SOIC D 8 2500 340.5 338.1 20.6
TL431ACDR SOIC D 8 2500 364.0 364.0 27.0
TL431ACDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431ACPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431ACPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL431AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431AIDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431AIDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0

Pack Materials-Page 6
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AIDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431AIDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431AIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431AIDBZTG4 SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431AIDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431AIDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431AIDR SOIC D 8 2500 364.0 364.0 27.0
TL431AIDR SOIC D 8 2500 340.5 338.1 20.6
TL431AIDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431AIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431AQDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431AQDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431AQDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431AQDBZRG4 SOT-23 DBZ 3 3000 202.0 201.0 28.0
TL431AQDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431AQDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431AQDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431AQDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431AQPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431BCDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431BCDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431BCDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BCDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BCDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BCDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431BCDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431BCDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431BCDBZTG4 SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431BCDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431BCDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431BCDR SOIC D 8 2500 340.5 338.1 20.6
TL431BCPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431BCPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL431BIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431BIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431BIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BIDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431BIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431BIDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431BIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0

Pack Materials-Page 7
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431BIDBZTG4 SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431BIDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431BIDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431BIDR SOIC D 8 2500 364.0 364.0 27.0
TL431BIDR SOIC D 8 2500 340.5 338.1 20.6
TL431BIDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431BIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431BQDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TL431BQDBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TL431BQDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431BQDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431BQDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431BQDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431BQDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431BQDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431BQDR SOIC D 8 2500 340.5 338.1 20.6
TL431CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431CDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431CDBVT SOT-23 DBV 5 250 183.0 183.0 20.0
TL431CDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431CDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431CDBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
TL431CDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431CDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431CDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431CDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431CDR SOIC D 8 2500 340.5 338.1 20.6
TL431CDR SOIC D 8 2500 364.0 364.0 27.0
TL431CDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431CPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431CPKE6 SOT-89 PK 3 1000 182.4 182.4 17.3
TL431CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TL431IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431IDBVR SOT-23 DBV 5 3000 183.0 183.0 20.0
TL431IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431IDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431IDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431IDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431IDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431IDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431IDR SOIC D 8 2500 364.0 364.0 27.0

Pack Materials-Page 8
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL431IDR SOIC D 8 2500 340.5 338.1 20.6
TL431IDRG4 SOIC D 8 2500 340.5 338.1 20.6
TL431IPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL431QDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431QDBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
TL431QDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TL431QDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL431QDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL431QDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL431QDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL431QDCKR SC70 DCK 6 3000 203.0 203.0 35.0
TL431QDCKT SC70 DCK 6 250 203.0 203.0 35.0
TL431QDR SOIC D 8 2500 340.5 338.1 20.6
TL432ACDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432ACDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432ACDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432ACDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432ACDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432AIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432AIDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432AIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432AIDBZTG4 SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432AIPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432AQDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TL432AQDBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TL432AQDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432AQDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432AQDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432AQDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432AQPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432BCDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432BCDBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TL432BCDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432BCDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432BCDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432BCDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432BCPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432BIDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432BIDBZRG4 SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432BIDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432BIDBZTG4 SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432BIPK SOT-89 PK 3 1000 340.0 340.0 38.0

Pack Materials-Page 9
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jun-2019

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL432BQDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432BQDBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432BQPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432CDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432CDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432CPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TL432IDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432IDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432IDBZT SOT-23 DBZ 3 250 180.0 180.0 18.0
TL432IDBZTG4 SOT-23 DBZ 3 250 183.0 183.0 20.0
TL432IPK SOT-89 PK 3 1000 340.0 340.0 38.0
TL432QDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0
TL432QDBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0
TL432QPK SOT-89 PK 3 1000 340.0 340.0 38.0

Pack Materials-Page 10
4203227/C
 PACKAGE OUTLINE
DBZ0003A SCALE 4.000
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR

2.64 C
2.10
1.12 MAX
1.4
B A
1.2 0.1 C
PIN 1
INDEX AREA

0.95
3.04
1.9 2.80
3

2
0.5
3X
0.3
0.10
0.2 C A B (0.95) TYP
0.01

0.25
GAGE PLANE 0.20
TYP
0.08

0.6
TYP SEATING PLANE
0 -8 TYP 0.2

4214838/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBZ0003A SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR

PKG
3X (1.3)
1

3X (0.6)

SYMM

3
2X (0.95)

(R0.05) TYP
(2.1)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214838/C 04/2017

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBZ0003A SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR

PKG

3X (1.3)
1

3X (0.6)

SYMM
3
2X(0.95)

(R0.05) TYP
(2.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:15X

4214838/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/D 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/D 11/2018

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/D 11/2018

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
6.6 SEATING PLANE
TYP
6.2

A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1

3.1 2X
2.9
NOTE 3 1.95

4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE

0.75 0.15
0 -8 0.05
0.50

DETAIL A
TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8

SYMM

6X (0.65)
5
4

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8

SYMM

6X (0.65)
5
4

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221848/A 02/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
LP0003A SCALE 1.200 SCALE 1.200
TO-92 - 5.34 mm max height
TO-92

5.21
4.44

EJECTOR PIN
OPTIONAL
5.34
4.32

(1.5) TYP

(2.54) SEATING
2X NOTE 3 PLANE
4 MAX
(0.51) TYP
6X
0.076 MAX
SEATING
PLANE
3X
12.7 MIN

0.43
2X 0.55 3X
3X 0.35
2.6 0.2 0.38
2X 1.27 0.13
FORMED LEAD OPTION
OTHER DIMENSIONS IDENTICAL STRAIGHT LEAD OPTION
TO STRAIGHT LEAD OPTION

2.67
3X
2.03 4.19
3.17
3 2 1

3.43 MIN

4215214/B 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.

www.ti.com
 EXAMPLE BOARD LAYOUT
LP0003A TO-92 - 5.34 mm max height
TO-92

FULL R
0.05 MAX (1.07) TYP
ALL AROUND METAL 3X ( 0.85) HOLE
TYP TYP

2X
METAL
(1.5) 2X (1.5)

2X
SOLDER MASK
OPENING
1 2 3
(R0.05) TYP 2X (1.07)
(1.27)
SOLDER MASK
(2.54)
OPENING

LAND PATTERN EXAMPLE

STRAIGHT LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X

0.05 MAX ( 1.4) 2X ( 1.4)

ALL AROUND METAL
TYP 3X ( 0.9) HOLE

METAL

2X
1 2 3 SOLDER MASK
(R0.05) TYP
(2.6) OPENING
SOLDER MASK
OPENING (5.2)

LAND PATTERN EXAMPLE

FORMED LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X

4215214/B 04/2017

www.ti.com
 TAPE SPECIFICATIONS
LP0003A TO-92 - 5.34 mm max height
TO-92

13.7
11.7

32
23

(2.5) TYP 0.5 MIN

16.5
15.5

11.0 9.75
8.5 8.50

19.0
17.5

2.9 6.75 3.7-4.3 TYP

TYP
2.4 5.95
13.0
12.4

FOR FORMED LEAD OPTION PACKAGE

4215214/B 04/2017

www.ti.com
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