DATASHEET

HI-7159A FN2936
Microprocessor-Compatible, 5-1/2 Digit A/D Converter Rev 4.00
January 1999

The Intersil HI-7159A is a monolithic A/D converter that uses Features

a unique dual slope technique which allows it to resolve input
changes as small as 1 part in 200,000 (10V) without the use • 200,000 Count A/D Converter
of critical external components. Its digital autozeroing feature • 2V Full Scale Reading With 10V Resolution
virtually eliminates zero drift over temperature. The device is
• 15 Conversions Per Second in 51/2 Digit Mode
fabricated in Intersil’ proprietary low noise BiMOS process,
resulting in exceptional linearity and noise performance. The • 60 Conversions Per Second in 41/2 Digit Mode
HI-7159A’s resolution can be switched between a high • Serial or Parallel Interface Modes
resolution 200,000 count (51/2 digit) mode, and a high speed
20,000 count (41/2 digit) mode without any hardware • Four Selectable Baud Rates
modifications. In the 41/2 digit uncompensated mode, speeds • Differential Analog Input
of 60 conversions per second can be achieved. The HI-7159A
• Differential Reference Input
is designed to be easily interfaced with most microprocessors
through either of its three serial and one parallel interface • Digital Autozero
modes. In the serial modes, any one of four common baud
rates is available. Applications
Ordering Information • Weigh Scales

TEMP. PKG.
• Part Counting Scales
PART NUMBER RANGE (oC) PACKAGE NO. • Laboratory Instruments
HI3-7159A-5 0 to 70 28 Ld PDIP E28.6 • Process Control/Monitoring
• Energy Management
• Seismic Monitoring

Pinout Functional Block Diagram

HI-7159A
(PDIP)
TOP VIEW
AGND VEE VCC XTAL DGND

VCC 1 28 SEL
INT OUT 2 27 XTAL
CINT INTEGRATOR COMPARATOR CONTROL
INT IN 3 26 DGND SECTION
- + AND 8 BIT
BUF OUT 4 25 P7/BRS1 + LATCHES BUS BUS
CREF-
- INTERFACE
5 24 P6/BRS0 RINT UNIT
GUARD
CREF- 6 23 P5/SAD3 BUFFER CS
+
I/O PORTS

CREF+ 7 22 P4/SAD2 -
WR
CREF+
8 21 P3/SAD1 VREF HI
GUARD
VREF HI 9 20 P2/SAD0 VREF LO RD

VREF LO 10 19 P1/SMS1 VIN HI UART

AGND 11 18 P0/SMS0 VIN LO ANALOG
ANALOG SWITCHES STATE
VIN HI 12 17 CS/SAD4 MACHINE
CREF SEL
VIN LO 13 16 WR/TXD
VEE 14 15 RD/RXD

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HI-7159A

Absolute Maximum Ratings Thermal Information

Supply Voltage Thermal Resistance (Typical, Note 1) JA (oC/W)
VCC to GND (AGND/DGND) . . . . . . . . . . . . . . -0.3V < VCC < +6V PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
VEE to GND (AGND/DGND) . . . . . . . . . . . . . . +0.3V < VCC < -6V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Digital Pins, (pins 15 - 28) . . . . . . . . DGND -0.3V < VD <VCC +0.3V Maximum Storage Temperature, TSTG . . . . . . . . . . -65oC to 150oC
Analog Pins, (pins 2 - 13). . . . . . . . . . VEE -0.3V < VA < VCC +0.3V Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Test Conditions: VCC = +5V, VEE = -5V, DGND = 0V, AGND = 0V, VREF HI = +1.00000V, VREF LO = AGND,
fCLOCK = 2.40MHz, RINT = 400k, CINT = 0.01F, TA = 25oC, VIN LO = AGND , CREF = 1.0F, 51/2 Digit
Compensated Mode, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Integral Non-Linearity, INL 0V to +2V (Notes 2, 3, 4, 5) - 0.0015 0.0035 % FS

-2V to 0V (Notes 2, 3, 4, 5) - 0.0015 0.0035 % FS

Ratiometric Reading VIN HI = VREF HI = 1.00000V 99996 100000 100003 Counts

Zero Error, ZE VIN HI = 0.00000V - 0 1 Counts

Voltage Range of VIN LO Input -2V  VIN HI - VIN LO  2V -1 - 1 V

(Pin 13), VIN LO

Voltage Range of VIN HI Input -2V  VIN HI - VIN LO  2V VIN LO-2V - VIN LO +2V V
(Pin 12), VIN HI

Common Mode Rejection, CMR VIN HI = VIN LO = -3V to +3V - 3 - Counts

Input Leakage Current, IIN Pins 9, 10, 12, 13, VIN = +3V, -3V - - 0.1 A

Input Capacitance, CIN Pins 9, 10, 12, 13 - 5 - pF

Noise (Peak-to-Peak Value, Not - 1 - Counts
Exceeded 95% of Time), eN

Zero Drift, TC(ZE) VIN HI = 0.00000V - 0 - Counts/oC

Full Scale Error Tempco, TC(FSE) VIN HI = 2.00000V - 0.1 - Counts/oC

Supply Range, VSUPPLY

VCC +4.75 +5.0 +5.5 V

VEE -4.75 -5.0 -5.5 V

VCC Supply Current, ICC - - 10 mA

VEE Supply Current, IEE - - 4.5 mA

Digital GND Current, IDGND - - 5.5 mA

Analog GND Current, IAGND - +3 - A

VCC , VEE Power Supply Rejection, VIN HI = VREF HI = 1.00000V, VCC = +4.75V, - 3 - Counts
PSR VEE = -4.75V to VCC = +5.50V, VEE = -5.50V

Guard Driver Pins 5, 8 VIN (Pins 9, 10) = +3V, -3V 10 - - A

Output Current, IOGD

NOTES:
2. All typical values have been characterized but are not production tested.
3. Not production tested, guaranteed by design and characterization.
4. Reference adjusted for correct full-scale reading.
5. VIN = VIN HI - VIN LO .

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HI-7159A

DC Electrical Specifications Test Conditions: VCC = +5V, VEE = -5V, DGND = 0V, AGND = 0V, VREF HI = +1.00000V, VREF LO =
AGND , fCLOCK = 2.40MHz, RINT = 400k, CINT = 0.01F, TA = 25oC, VIN LO = AGND , CREF = 1.0F,
51/2 Digit Compensated Mode, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input Low Voltage, VIL Pins 15-25, 28 - - 0.8 V

Input High Voltage, VIH Pins 15-25, 28 2.0 - - V

Output Low Voltage, VOL Pins 16, 18-25, IOL = 1.6mA - - 0.4 V

Output High Voltage, VOH Pins 16, 18-25, IOH = -400A 2.4 - - V

Three-State Leakage Current, All Digital Drivers In High Impedance State, - - 10 A
Pins 18-25, IOL Parallel Mode. CS = VCC , VIN = 0V, VCC

Leakage, Pins 15-17, 28, IIN VIN = 0V, VCC - - 1 A

Input Capacitance, CIN Pins 15, 17-25, 28 - 5 - pF

Pin 16 - 10 - pF

Input Pullup Current (Pins 18-25), IPU Pins 18-25 at DGND - -5 - A

SEL = DGND (Serial Modes)

AC Electrical Specifications TA = 0oC to 75oC; Test Conditions: VCC = +4.75V, VEE = -5.00V (Note 8), DGND = 0V, AGND = 0V,
VIN LO = AGND , VREF HI = +1.00000V, VREF LO = AGND , fCLOCK = 2.40MHz, RINT = 400k ,
CINT = 0.01F, VIL = 0V, VIH = 4V, VOL = VOH = 1.5V, tr = tf < 10ns, 51/2 Digit Compensated Mode,
Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CS Setup/Hold of WR, t1 0 - - ns

WR Setup of Data In, t2 50 - - ns

WR Pulse Width, t3 150 - - ns

Data Hold After WR, t4 20 - - ns

CS Setup/Hold of RD, t5 (Note 7) 25 - - ns

RD to Data Out, t6 CL = 50pF, VO = 1.5V - - 100 ns

RD to Hi-Z State, t7 - - 70 ns

WR to RD, WR to WR, tA (Note 7) 5/fCLOCK - - s

RD to WR, tB (Note 7) 200 - - ns

RXD Setup of Data In, tC (Note 7) 60 - - ns

Data Hold After EXT CLK, tD 40 - - ns

EXT CLK to DATA OUT, tE - - 300 ns

CS Setup of TXD, tf 100 - - ns

NOTES:
6. All typical values have been characterized but are not production tested.
7. Not production tested, guaranteed by design and characterization.
8. All AC characteristics are guaranteed for VCC = +5V 15%, VEE = -5V 15%, over TA = 0oC to 75oC.

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Timing Waveforms
CS

t1 t3 t1
WR WR
tA
t2 t4
RD
P0 - P7 DATA IN

FIGURE 1A. WRITE FIGURE 1B. WRITE TO READ CYCLE

WR
tA

FIGURE 1C. WRITE TO WRITE CYCLE

CS
t5 t5 RD
RD tB
WR
t6 t7

P0 - P7 DATA OUT

FIGURE 1D. READ FIGURE 1E. READ TO WRITE CYCLE

FIGURE 1. PARALLEL MODE TIMING

CLK
(PIN 15)

RXD/TXD D0 D1 D2 D3 D4 D5 D6 D7
(PIN 16) tC (HI-7159A RECEIVING)
tD

RXD/TXD D0 D1 D2 D3 D4 D5 D6 D7
(PIN 16) (HI-7159A TRANSMITTING)
tE

FIGURE 2A. SERIAL MODE 0 TIMING

CS
(SERIAL MODE 1)
tf

TXD OR RXD START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP

DATA CLOCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BIT DETECTOR
SAMPLE TIME

NOTE: All input timing shown is defined at 50% points.

FIGURE 2B. SERIAL MODE TIMING

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Pin Descriptions
PIN SYMBOL DESCRIPTION
1 VCC Positive 5V Power Supply for analog and digital sections.
2 INT OUT Integrator Output; external component terminal.
3 INT IN Integrator Input; external component terminal.
4 BUF OUT VIN HI Voltage Buffer Output; external component terminal.
5 CREF - Guard Reference Capacitor guard ring terminal (negative).
6 CREF - Reference Capacitor negative terminal.
7 CREF + Reference Capacitor positive terminal.
8 CREF + Guard Reference Capacitor guard ring terminal (positive).
9 VREF HI Positive Reference Input terminal.
10 VREF LO Negative Reference Input terminal.
11 AGND Analog Ground (0V).
12 VIN HI Positive Analog Input Voltage terminal.
13 VIN LO Negative Analog Input Voltage terminal.
14 VEE Negative 5V Power Supply for analog section.
15 RD/RXD Parallel Read; serial receive (modes 1 and 2), serial clock (mode 0).
16 WR/TXD Parallel Write; serial transmit (modes 1 and 2), serial receive/transmit (mode 0).
17 CS/SAD4 Chip Select (parallel and serial modes 0 and 1), serial address bit 4 (mode 2).
18 P0/SMS0 Parallel I/O Port (P0); serial mode select pin.
19 P1/SMS1 Parallel I/O Port (P1); serial mode select pin.

MODE SMS0 SMS1

Serial Mode 0 0 0

Serial Mode 1 0 1

Serial Mode 2 1 0

Reserved 1 1

20 P2/SAD0 Parallel I/O Port (P2); serial address bit 0.

21 P3/SAD1 Parallel I/O Port (P3); serial address bit 1.
22 P4/SAD2 Parallel I/O Port (P4); serial address bit 2.
23 P5/SAD3 Parallel I/O Port (P5); serial address bit 3.
24 P6/BRS0 Parallel I/O Port (P6); serial baud rate select.
25 P7/BRS1 Parallel I/O Port (P7); serial baud rate select.

BAUD RATE BRS0 BRS1

300 0 0
1200 0 1

9600 1 0

19200 1 1

26 DGND Digital Ground (0V).

27 XTAL Oscillator Out; crystal connection pin (other crystal pin connected to VCC).
28 SEL Select pin for parallel or serial operation.
Parallel SEL = 1
Serial Modes SEL = 0

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Theory of Operation Communication Modes

The HI-7159A attains its 51/2 digit resolution through the use of The HI-7159A A/D converter receives instructions from and
multiple integrations per conversion, creating an effective transmits data to the user host processor through one of four
integrator swing greater than the supply rails, and a successive communication modes. The modes are: parallel microprocessor
integration technique used to measure the residue on the (Parallel); synchronous serial (Serial Mode 0); serial non-
integrator capacitor to 51/2 digit accuracy. addressed (Serial Mode 1); and serial addressed (Serial Mode
In the 51/2 digit mode, the input voltage is integrated and 2). The mode is determined by the states of the SEL, SMS0, and
reference de-integrated four times. This results in a count with the SMS1 pins as shown in Table 1.
same effective resolution as a single integration with four times The parallel mode allows the converter to be attached directly to
the integrator swing amplitude. In this manner effective integrator a microprocessor data bus. Data is read and written to the
swings of 12V or greater can be achieved with 5V supplies. device under control of the microprocessor’s RD, WR and CS
The four integrations are spaced so that common-mode signals signals. Serial Mode 0 permits high speed serial data transfer at
whose frequency is an integer multiple of fCRYSTAL/40,000 are up to 1 megabits/s. Serial Mode 1 reads and writes industry
rejected. In the 41/2 digit mode, only one input integration is standard serial data packets consisting of 1 start bit, 8 data bits,
performed, thus the minimum frequency for common-mode 1 parity bit (EVEN), and 1 stop bit, at one of 4 hardware
rejection becomes fCRYSTAL/10,000. selectable baud rates. Serial Mode 2 is identical to Serial Mode
These first four integrations measure the input voltage to an 1 with the addition of addressing capabilities which allow up to
resolution of 31/2 digits, or 1mV/count. To achieve 51/2 digit 32 HI-7159As to share the same serial line, with each assigned
accuracy (10V/count), the error voltage remaining on the a unique address.
integrator capacitor (representing the overshoot of the TABLE 1. COMMUNICATION MODE SELECTION
integrator due to comparator delay and clock quantization)
SEL PIN SM S0 SM S1
must be measured and subtracted from the 31/2 digit result. COMMUNICATION MODE 28 PIN 18 PIN 19
This is accomplished by multiplying the residue by a factor of
Parallel VCC N/A N/A
10, then integrating and reference de-integrating the error. This
error is subtracted from the 31/2 digit result, yielding a 41/2 digit Serial 0 DGND DGND DGND
accurate result. The error remaining from this step is then Serial 1 DGND DGND VCC
multiplied by 10 and subtracted, and the process is repeated a
Serial 2 DGND VCC DGND
third time to achieve an internal accuracy of 61/2 digits. This
result is rounded to 51/2 digits and transferred to the holding
All four modes follow the same interface protocol: a request or
register, where it can be accessed by the user through one of
a command is sent from the host to the HI-7159A, and the
the three communications modes.
converter responds with the requested data and, in the case of
Conversion Types a command, begins a new conversion.
The HI-7159A offers the user a choice of three different Parallel Mode Operation
conversion types. They are: (1) the converter’s internal offset
The parallel communication mode (Figure 3) is selected when
voltage, measured by internally connecting VIN HI and VIN LO to
SEL (Pin 28) is high. Pins 18-25 become the eight bidirectional
AGND and doing a conversion (Error Only Mode); (2) the input
data bits, P0-P7. Pins 15, 16, and 17 respectively become read
voltage (VIN HI minus VIN LO) including the converter’s internal
(RD), write (WR), and chip select (CS). Timing parameters for
offset (Uncompensated Mode); and (3) the input voltage including
the parallel mode are shown in Figure 1.
internal offset errors, minus the internal offset errors
(Compensated Mode). This last measurement is a digital Serial Mode 0
subtraction of an Error Only conversion from an Uncompensated Serial Mode 0 is the high speed synchronous serial interface,
conversion, and is the default conversion type. Since a directly compatible with the MCS-51 series of microcontrollers. It
Compensated conversion consists of two conversions, it takes is enabled by tying SEL (Pin 28), SMS0 (Pin 18) and SMS1 (Pin
twice as long to perform as the first two types. 19) low (Figure 4A). Pin 16 is the bidirectional serial data path,
Under some conditions, it may be desirable to increase the and pin 15 is the data clock input. Data sent to the HI-7159A is
conversion rate without loss of resolution or accuracy. Since latched on the rising edge of the serial clock. See Figure 2A for
the short term drift of the internal offset error is slight when detailed timing information.
temperature is controlled, it is not always necessary to convert Only 8 data bits are used in this mode - no start, stop, or parity
the error voltage once for every input voltage conversion. It is bits are transmitted or received. CS must either be tied to
possible for the host processor to do an error conversion DGND or pulled low to access the device. The SAD0 - SAD3
periodically, store the result, and subtract the error from a and BRS0 - BRS1 pins are unused in this mode and should be
stream of uncompensated input conversions with its own tied high.
internal ALU. In this way the conversion rate can be effectively
doubled.

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HI-7159A

Serial Mode 1
-5V +5V
Serial Mode 1 is selected by tying SMS0 (Pin 18) low, SMS1
(Pin 19) high, and SEL (Pin 28) low (Figure 4B). In this mode VEE VCC
the HI-7159A interface emulates a UART, reading and writing 14 1 XTAL
CLK CLK
data in serial data packets of 1 start bit, 8 data bits, 1 parity bit 10
RXD/TXD RXD/TXD
15
(EVEN), and 1 stop bit. The baud rate is determined by the 11 16 27
XTAL
state of BRS0 and BRS1 (Pins 24 and 25) as shown in Table
2. Pin 15 becomes the serial receiver pin (RXD) and pin 16 the 8051
HI-7159A
P +5V
serial transmitter pin (TXD). CS (Pin 17) remains a chip select
and must either be tied to DGND or pulled low (see Figure 2B) SM0
18 20-25
to access the device. SAD0-SAD3 (Pins 20-23) are unused in SM1
19
this mode and should be tied high. 17 26 28

TABLE 2. BAUD RATE SELECTION FOR MODES 1 AND 2 CS DGND SEL

BRS0 BRS1 BAUD RATE BAUD RATE vs

PIN 24 PIN 25 (fXTAL = 2.4576MHz) fXTAL
DGND DGND 300 fXTAL/8192 FIGURE 4A. SERIAL MODE 0

DGND VCC 1200 fXTAL/2048

-5V +5V
VCC DGND 9600 fXTAL/256
VCC VCC 19200 fXTAL/128 VEE VCC
TXD RXD 14 1 XTAL
RXD TXD 15
16 27
-5V +5V +5V XTAL

VEE SEL VCC 20K 20K

UART/P
BRS0 HI-7159A
P RD RD 14 28 1 XTAL 24 +5V
15 BRS1
WR WR 25
16 27 SM0
18 20 - 23
+5V
ADDRESS SM1
ADDRESS CS 19
17 HI- 7159A
DECODER 17 26 28
BUS
D0 D0 CS DGND SEL
DATA 18

BUS 25
D7 D7 26
FIGURE 4B. SERIAL MODE 1
DGND

FIGURE 3. PARALLEL MODE CONFIGURATION TO UP TO 31 ADDITIONAL

HI-7159As
-5V +5V
Design Hints for Operating in the Parallel
VEE VCC
Mode TXD RXD 14 1 XTAL
1. Always read the status byte twice to make sure that it is 15
RXD TXD
cleared. 16 27
+5V XTAL
2. Make sure the status byte is cleared before issuing a
command to change modes. 20K 20K
BRS0 HI-7159A
3. Read each digit pair five times before reading the next byte UART/P 24
BRS1 20
to ensure that the output data is correct. 25 21 ADDRESS
+5V 22 SELECT
4. Use a watchdog timer to monitor conversion time. If SM0 23
18 17
conversion time is either too long or too short, reissue the SM1
19
conversion command. 26 28
DGND SEL

FIGURE 4C. SERIAL MODE 2

FIGURE 4. SERIAL MODE CONFIGURATIONS

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HI-7159A

Serial Mode 2 conversion (Compensated, Uncompensated, or Error Only). Bit

Serial Mode 2 is selected by tying SEL (pin 28) low, SMS0 (pin D0 = 0 indicates that this is a command byte and a new
18) high, and SMS1 (pin 19) low, as shown in Figure 4C. This conversion(s) should be started.
mode of operation is identical to Serial Mode 1, except that A request byte (Table 6) asks for either the status of the
each device now has one of 32 unique addresses determined converter or the result of a conversion. All bits of a request
by the state of pins 20-23 and 17, as shown in Table 3. This should be set to 0 except D3, D2, and D0. D3 and D2
allows multiple HI-7159As to be attached to the same pair of determine the type of request (status or digit pair), and D0 = 1
serial lines. indicates to the HI-7159A that this is a request byte. Serial
When the microprocessor sends out an Address Byte (Table 4) Mode 2 uses a slightly modified request byte, shown in Table
that matches one of the HI-7159As’ hardwired addresses, that 7, allowing it to individually select each of the six digit bytes.
particular HI-7159A is selected for all further I/O until another Upon receipt of a request, the HI-7159A will respond with
Address Byte with a different address is transmitted. either a status or a digit byte. The status byte (Table 8) returns
the current state of the converter. Bit D6 = 1 indicates that a
TABLE 3. HARDWARE ADDRESS SELECTION FOR MODE 2
new conversion has been completed since the last time the
PIN 17 PIN 23 PIN 22 PIN 21 PIN 20 status byte was read. Bit D6 is cleared after it is read. Bit D4
B4 (MSB) B3 B2 B1 B0 (LSB) shows the current continuity (single or continuous). Bit D3
indicates the resolution (51/2 or 41/2 digits) of the conversion,
Reading the HI-7159A and bits D2 and D1 indicate the type (Compensated,
Despite the wide variety of interface options available on the Uncompensated, or Error Only). Bit D0 = 0 indicates that there
HI-7159A, the procedure for communicating with it is was no parity error detected in the last request byte.
essentially the same in all four modes. (Serial Mode 2 differs The three digit bytes (Table 9) each contain two nibbles
from the rest in two respects: the chip to be communicated with representing two digits of the conversion. The sixth nibble
must first be sent an address byte to select it, and the digit contains the MSD (most significant digit), polarity (1 = positive)
bytes are sent one by one, for a total of six bytes, instead of in and overrange (1 = overrange) information. In Serial Mode 2
pairs.) There are two types of bytes that can be sent to the the digits (Table 10) are requested and received individually,
converter, commands and requests. A command byte (Table so a total of six requests and six reads is necessary to obtain
5) sets the parameters of and initiates a conversion. Those all 51/2 digits.
parameters are: continuity of the conversion (single or
continuous), resolution (51/2 or 41/2 digits), and type of

TABLE 4. SERIAL MODE 2 ADDRESS BYTE FORMAT (SENT TO HI-7159A)

ADDRESS BIT (RESERVED) (MSB) (LSB)

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 B4 B3 B2 B1 B0

TABLE 5. COMMAND BYTE FORMAT (SENT TO HI-7159A)

(RESERVED) CONTINUITY RESOLUTION CONVERSION TYPE COMMAND BIT

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 Single 0 51/ 2 1 Comp 1 1 0

Continuous 1 41/ 2 0 Uncomp 1 0

Error Only 0 1

TABLE 6. REQUEST BYTE FORMAT, PARALLEL AND SERIAL MODE 1 (SENT TO HI-7159A)

(RESERVED) BYTE REQUEST (RESERVED) REQUEST BIT

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 Digit Pair 0, 1 0 0 0 1

Digit Pair 2, 3 0 1

Digit Pair 4, 5 1 0

Converter Status 1 1

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TABLE 7. REQUEST BYTE FORMAT, SERIAL MODE 2 (SENT TO HI-7159A)

(RESERVED) BYTE REQUEST REQUEST BIT

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 Digit 0 0 0 0 1

Digit 1 0 0 1

Digit 2 0 1 0

Digit 3 0 1 1

Digit 4 1 0 0

Digit 5 1 0 1

Converter Status 1 1 0

TABLE 8. STATUS BYTE FORMAT (RECEIVED FROM HI-7159A)

CONVERTER PARITY
(†) UPDATE STATUS (†) CONTINUITY RESOLUTION CONVERSION TYPE ERROR

D7 D6 D5 D4 D3 D2 D1 D0

0 No Update 0 0 Single 0 5 1 /2 1 Comp 1 1 No 0

Updated 1 Continuous 1 4 1/ 2 0 Uncomp 1 0 Yes 1

Error 0 1

(† = Reserved)

TABLE 9. DIGIT BYTE FORMAT, PARALLEL AND SERIAL MODE 1 (RECEIVED FROM HI-7159A)

DIGIT BYTE D7 D6 D5 D4 D3 D2 D1 D0

Digit Pair 0, 1 MSB1 LSB1 MSB0 LSB0

Digit Pair 2, 3 MSB3 LSB3 MSB2 LSB2

Digit Pair 4, 5 Polarity Overrange MSB5 LSB5 MSB4 LSB4

(1 = POS) (1 = OR)

TABLE 10. DIGIT BYTE FORMAT, SERIAL MODE 2 (RECEIVED FROM HI-7159A)

DIGIT BYTE D7 D6 D5 D4 D3 D2 D1 D0

Digits 0 - 4 0 0 1 1 MSB LSB

Digit 5 0 0 1 1 Polarity Overrange MSB LSB

(1 = POS) (1 = OR)

Single Conversion Mode Continuous Conversion Mode

The suggested algorithm for reading the HI-7159A in its single Once a command byte is sent to the HI-7159A initiating the
conversion mode of operation is shown in Figure 5. Essentially continuous conversion mode, the output data registers will be
it consists of initiating a conversion, waiting until the updated continuously after every conversion. This makes
conversion is complete, and then reading the results. Since no obtaining a valid reading more difficult, since the possibility
further conversions take place, the data may be read out at exists that the current data could be overwritten by a new
any time and at any speed. This is the most straightforward conversion before all the digit bytes are read. To prevent this,
method of reading the HI-7159A. the status byte should be read before and after the data is read
from the converter, to ensure that the converter has not updated
during the reads. This is demonstrated in Figure 6.

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HI-7159A

50% range indicate that it is possible to get valid data out with
SEND COMMAND BYTE very tight code. In all cases the status byte should be checked
(INITIATE SINGLE CONVERSION)
before and after the reading to ensure data integrity.

TABLE 11. SERIAL MODES 1/2

GET STATUS BYTE
CONVERSION TYPE

BAUD 5 1 /2 4 1 /2
NO RATE 51/2 COMP UNCOMP 41/2 COMP UNCOMP
D6 = 1?
300 * /* * /* * /* * /*
1200 54%/* * /* * /* * /*
YES
9600 7%/13% 14%/25% 27%/50% 54%/*
GET DIGIT BYTES
19200 4%/7% 7%/13% 14%/25% 27%/50%

CONVERSION RESULT Crystal Oscillator

IS VALID
The HI-7159A uses a single pin crystal oscillator design
FIGURE 5. READING THE HI-7159A IN THE SINGLE (Figure 7). The crystal is connected between Pin 27 and
CONVERSION MODE VCC ; no load capacitors or other components are necessary.
The user has a choice of crystal frequencies: 2.4576MHz or
2.4MHz. An off-the-shelf 2.4576MHz crystal works well and
GET STATUS BYTE provides baud rates of exactly 19.2K, 9600, 1200, and 300.
However its total integration period will be 16.28ms, or
0.39ms shorter than a 60Hz cycle. This effectively reduces
the normal mode AC rejection.
NO
D6 = 1?
+5V

VCC

YES 1 CRYSTAL
(2MHz TO 2.5MHz)
GET DIGIT BYTES
HI-7159A 27
XTAL

GET STATUS BYTE FIGURE 7. SINGLE-PIN OSCILLATOR

A 2.4MHz crystal results in an integration period of 16.67ms,

exactly the length of one 60Hz AC cycle. Normal mode AC
rejection is greatest at this frequency. At 2.4MHz, however, the
CONVERSION
CONVERSION YES NO RESULT MAY Baud rates will be off by -2.34%. This error is not large enough
RESULT IS D6 = 0? BE INVALID: to cause any errors with most peripherals, and only applies to
VALID DISCARD
RESULT operation in Serial Modes 1 and 2. Communication in Serial
Mode 0 and the Parallel Mode is independent of the crystal
frequency. For this mode a 2.4MHz crystal is recommended.
FIGURE 6. READING THE HI-7159A IN THE CONTINUOUS
While the oscillator was designed to operate at
CONVERSION MODE
2MHz - 2.5MHz, the HI-7159A itself will operate reliably down
to less than 600kHz when driven with an external clock.
Due to the wide range of baud rates available in the serial modes,
Benefits at lower clock frequencies include reduced rollover
some of the lower baud rates will take longer to transfer the output
error (gain error for negative input voltages) and lower noise.
data than it takes to perform a conversion. In these cases the
The baud rates mentioned throughout this data sheet
continuous mode should not be used. Table 11 shows the
correspond to a crystal frequency of 2.4576MHz. At 1.2MHz,
percentage of the total conversion time that it takes to read all the
the actual baud rates will be half the speed they were at
data from the converter for the two serial modes. These are best
2.4MHz, i.e., 9600, 4800, 600 and 150 baud. At 600kHz they
case numbers, assuming that the bytes are transmitted and
will be one-fourth.
received end-to-end. An asterisk indicates that it is impossible to
get all the data out within one conversion. Percentages in the 20-

FN2936 Rev 4.00 Page 10 of 14

January 1999
HI-7159A

It may also be possible to directly program the host’s serial +5V

hardware for operation at nonstandard baud rates, allowing -5V
HI-7159A operation at any arbitrary frequency. For example: VCC XTAL
50Hz AC rejection requires a 2MHz clock. At this frequency the 1 27 VEE
“9600” baud rate becomes 7812.5 baud. The host’s UART 14
must be programmed with the proper divider to operate at this CINT
INT OUT
baud rate. The data clock (see Figure 2) is defined as 16 times 2
VREF HI
the baud rate, so the data clock of this configuration would be 9 INT IN
VREF LO 3
125kHz. The data clock can also be determined by dividing the RINT
10 BUF OUT
oscillator (clock) frequency by the correct divider from Table 4
HI-7159A
12. VIN HI
CREF - GUARD
12
5
TABLE 12. CRYSTAL DIVIDER RATIOS VIN LO
13 CREF-
6 REFERENCE
BAUD RATE SELECTED CRYSTAL DIVIDER CREF
CAPACITOR
CREF+ GUARD
“300” 512 RINGS
7
“1200” 128 AGND
11 26 8
“9600” 16 CREF+ GUARD

“19200” 8 DGND
AGND DGND
The following equation determines the divider needed to
FIGURE 8. ANALOG COMPONENTS AND INPUTS
operate the HI-7159A at any given crystal frequency:
TABLE 14. RECOMMENDED COMPONENT VALUES vs CLOCK
f CLOCK  7159A  f CRYSTAL  Host UART  FREQUENCY
-------------------------------------------- = ---------------------------------------------------------------- = Data Clock
Divider  7159A  Divider  Host UART 
fCLOCK RINT CINT CREF
Once determined, the new divider must be written directly to the
2.4MHz 400k 0.01F 1.0F
Host’s UART. Most PC compatibles use an 8250 UART with a
1.8432MHz crystal, so the proper divider for the 2MHz example 1.2MHz 360k 0.022F 2.2F
given above would be 15. Again, these considerations apply only 600kHz 330k 0.047F 4.7F
to Serial Modes 1 and 2. Parallel and Serial Mode 0
NOTE: CINT MUST be a high quality polypropylene capacitor or
communication rates are independent of crystal frequency.
performance may be degraded.
Conversion Time The reference capacitor and integrating components can either
The conversion time of the HI-7159A is a function of the crystal be selected from Table 14, or calculated from the following
frequency and the type of conversion being made. The equations.
conversion times for fCLOCK = 2.4MHz are shown in Table 13.
CREF acts as a voltage source at different times during a
At other clock frequencies the times may be calculated from
conversion. Its value is determined by two considerations: it
the following formula:
must be small enough to be fully charged from its discharged
C state at power-on; yet it also must be large enough to supply
t CONV = ---------------------
f CLOCK
current to the circuit during conversion without significantly
where the constant C is determined from Table 13. drooping from its initial value. For 2.4MHz operation, a 1F
capacitor is recommended. The equation for other
TABLE 13. CONVERSION TIMES frequencies is:
CONVERSION TYPE
2.5
51/ 51/2 41/2 41/2 C REF = ---------------------
2 f CLOCK
COMP UNCOMP COMP UNCOMP
f = 2.4MHz 133ms 66.7ms 33.3ms 16.7ms The values of RINT and CINT are selected by choosing the
maximum integration current and the maximum integrator
C 320,000 160,000 80,000 40,000
output voltage swing. The maximum integration current and
Component Selection voltage swing occurs when VIN = full scale = 2 X VREF . The
recommended integration current for the HI-7159A is
Three external passive components must be chosen for the
5mA - 10mA. This will help determine the value of RINT , since:
HI-7159A: the integrating capacitor (CINT), the integrating resistor
V IN V IN
(RINT), and the reference capacitor (CREF). They are chosen I INT = ------------- so R INT = ----------- ,
R INT I INT
based on the crystal frequency, the reference voltage (VREF), and
the desired integrating current. Figure 8 illustrates the analog where VIN = VIN HI - VIN LO = 2 x VREF .
components necessary for the HI-7159A to function.

FN2936 Rev 4.00 Page 11 of 14

January 1999
HI-7159A

Therefore values of RINT should be between 200k and 200,000

400k. The exact value of RINT may be altered to get the
exact integrator swing desired after choosing a standard
capacitor value for CINT . 100,000

The most critical component in any integrating A/D converter is

OUTPUT COUNT
the integrating capacitor, CINT . For a converter of this
000,000
resolution, it is imperative that this component perform as
closely to an ideal capacitor as possible. Any amount of
leakage or dielectric absorption will manifest itself as linearity
-100,000
errors. For this reason CINT must be a high quality
-200,012
polypropylene capacitor. Use of any other type may degrade COUNTS
performance. The value of CINT is determined by the -200,000
magnitude of the desired maximum integrator output voltage
swing as shown below: -2 -1 0 1 2
INPUT (V)
 V IN   t INT  FIGURE 9. TYPICAL HI-7159A TRANSFER CHARACTERISTIC
V SWING = -------------------------------------
 R INT   C INT 
CREF Guard Pins
Solving for CINT yields: Depending on the polarity of the input signal, either the
negative or the positive terminal of the reference capacitor
 V IN   t INT 
C INT = ----------------------------------------------- will be connected to AGND to provide the correct polarity for
 R INT   V SWING 
reference deintegration. In systems where VREF LO is tied to
analog ground, the reference capacitor is effectively shifted
where VSWING is the maximum output voltage swing of the down by | VREF | for positive input voltages, and is not shifted
integrator, VIN is the full scale input voltage (VIN HI - VIN LO) to at all for negative input voltages. This shift can cause some
the converter (equal to 2 X VREF), and tINT is the time in which charge on the reference capacitor to be lost due to stray
VIN is integrated. The best results are achieved when the capacitance between the reference capacitor leads and
maximum integrator output voltage is made as large as ground traces or other fixed potentials on the board. The
possible, yet still less than the nonlinear region in the vicinity of reference voltage will now be slightly smaller for positive
the power supply limit. A full scale output swing of about 3V inputs. This difference in reference voltages for positive and
provides the greatest accuracy and linearity. negative inputs appears as rollover error.
NOTE: The integrator is auto-zeroed to the voltage at VIN LO . If VIN The HI-7159A provides two guard ring outputs to minimize this
LO is negative with respect to AGND , the integrator will have | VIN LO | effect. Each guard ring output is a buffered version of the
less headroom for positive input voltages (inputs where VIN HI - VIN LO voltage at its respective CREF pin. If the traces going to the
> 0). If VIN LO is positive with respect to AGND , the integrator will have
CREF pins and under CREF itself are surrounded by their
| VIN LO | less headroom for negative input voltages (inputs where VIN
corresponding guard rings, no charge will be lost as CREF is
HI - VIN LO < 0). In most applications VIN LO is at or near AGND and the
above equations will be adequate. In applications where VIN LO may be moved. Figure 10 shows two slightly different patterns. The
more than 0.1V away from AGND , it should be included in the integrator first one is for capacitors of symmetrical construction, the
swing considerations. The following formula combines all the above second is for capacitors with outside foils (one end of the
considerations:.
capacitor is the entire outside.
 V IN HI – V IN LO   10 000 
V IN LO – -----------------------------------------------------------------------  3V
R INT C INT f OSC  (5) CREF- GUARD

(6) CREF-
Gain Error Adjustments HI -7159A
(7) CREF+
While the HI-7159A has a very linear transfer characteristic in
both the positive and negative directions, the slope of the line (8) CREF+ GUARD

is slightly greater for negative inputs than for positive. This

results in the transfer characteristic shown in Figure 9. One
(5) CREF- GUARD
end point of this curve, typically the positive side, can be
(6) CREF-
adjusted to zero error by trimming the reference voltage. The
HI -7159A
other (negative) side will have a fixed gain error. This error can (7) CREF+
be removed in software by multiplying all negative readings by (8) CREF+ GUARD
a scale factor, determined by dividing the ideal full scale
reading (-200,000 counts) by the actual full scale reading when
FIGURE 10. TYPICAL GUARD RING LAYOUT
VIN = -2.00000V.

FN2936 Rev 4.00 Page 12 of 14

January 1999
HI-7159A

Die Characteristics PASSIVATION:

Type: PSG/Nitride
DIE DIMENSIONS:
Thickness: 15kÅ 1kÅ
5817m x 3988m
Metallization Mask Layout
METALLIZATION:
Type: SiAl
Thickness: 10kÅ 1kÅ
HI-7159A

BUF INT INT

OUT IN OUT VCC VCC SEL XTAL DGND

P7/BRS1

P6/BRS0

CREF -
GUARD P5/SAD3

P4/SAD2

P3/SAD1
CREF -

CREF + P2/SAD0

P1/SMS1

CREF +
GUARD
VREF
HI
VREF P0/SMS0
LO

AGND VIN VIN VEE RD/RXD WR/TWD CS/SAD4

HI LO

FN2936 Rev 4.00 Page 13 of 14

January 1999
HI-7159A

Dual-In-Line Plastic Packages (PDIP)

E28.6 (JEDEC MS-001-BF ISSUE D)
N 28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
E1 PACKAGE
INDEX
AREA 1 2 3 N/2
INCHES MILLIMETERS
-B- SYMBOL MIN MAX MIN MAX NOTES
-A- A - 0.250 - 6.35 4
D E
A1 0.015 - 0.39 - 4
BASE
PLANE A2 A2 0.125 0.195 3.18 4.95 -
-C- A
SEATING B 0.014 0.022 0.356 0.558 -
PLANE L C
L
B1 0.030 0.070 0.77 1.77 8
D1 A1 eA
D1 C 0.008 0.015 0.204 0.381 -
B1 e
eC C
B D 1.380 1.565 35.1 39.7 5
eB
0.010 (0.25) M C A B S D1 0.005 - 0.13 - 5

NOTES: E 0.600 0.625 15.24 15.87 6

1. Controlling Dimensions: INCH. In case of conflict between English and E1 0.485 0.580 12.32 14.73 5
Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA 0.600 BSC 15.24 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95. eB - 0.700 - 17.78 7
4. Dimensions A, A1 and L are measured with the package seated in L 0.115 0.200 2.93 5.08 4
JEDEC seating plane gauge GS-3. N 28 28 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Rev. 0 12/93
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendic-
ular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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FN2936 Rev 4.00 Page 14 of 14

January 1999