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Logic Diagram by VHDL Code (RTL Viewer)

The document discusses a Logic Diagram created using VHDL code and includes references to RTL Viewer and Technology Map Viewer designs. It also mentions simulation files with specific time markers at 22ns, 42.5ns, 80ns, and 158.8ns. However, detailed content regarding the simulations or diagrams is not provided.

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FAseeh Malik
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46 views3 pages

Logic Diagram by VHDL Code (RTL Viewer)

The document discusses a Logic Diagram created using VHDL code and includes references to RTL Viewer and Technology Map Viewer designs. It also mentions simulation files with specific time markers at 22ns, 42.5ns, 80ns, and 158.8ns. However, detailed content regarding the simulations or diagrams is not provided.

Uploaded by

FAseeh Malik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Logic Diagram by VHDL code (RTL Viewer)

Technology Map Viewer Design


.wav Simulation Files

At 22ns:

At 42.5ns:

At 80ns:
At 158.8ns:

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