SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
18CSS201J-ANALOG AND DIGITAL ELECTRONICS
QUESTION BANK – UNIT - III
Part – A (Each Question Carries 1 mark)
Level 1- PART A
1. The device which changes from serial data to parallel data is
(A) Counter
(B) Multiplexer
(C) Demultiplexer
(D) Flip flop
ANSWER: (C)
2. A device which converts BCD to Seven Segment is called
(A) Encoder
(B) Decoder
(C) Multiplexer
(D) Demultiplexer
ANSWER: (B)
3. To secure a higher speed of addition, which of the following is the preferred solution?
(A) serial adder
(B) parallel adder
(C) adder with a look-ahead carry
(D) full adder
ANSWER: (C)
4. What is the largest number of data input which a data selector with two control inputs can
have?
(A) 2
(B) 4
(C) 8
(D) 16
ANSWER: (B)
5. Which one of the following set of gates is best suited for parity checking and parity
generation?
(A) AND , OR , NOT gates
(B) Ex-NOR , Ex-OR gates
(C) NAND gate
(D) AND gate
ANSWER: (B)
6. A decoder can be used as a demultiplexer by
(A) Tying all enable pins low
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
(B) Tying all data select lines low
(C) Tying all data select lines high
(D) Using the inputs lines for data selection and an enable line for data input
ANSWER: (D)
7. A combinational circuit with n inputs and maximum of 2n outputs is
(A) Encoder
(B) Decoder
(C) Multiplexer
(D) Demultiplexer
ANSWER: (C)
8. In error detecting/error correcting applications , the device which is most useful is
(A) Comparator
(B) Multiplexer
(C) Parity generator
(D) Demultiplexer
ANSWER: (C)
9. How many inputs are required for a 1-of-10 BCD decoder?
(A) 4
(B) 8
(C) 12
(D) 10
ANSWER: (A)
10.The number of control lines for an 8 to 1 multiplexer
(A) 1
(B) 2
(C) 3
(D) 4
ANSWER: (C)
11. In 4 bit parallel adder initial carry (Cin) is set as
(A) 0
(B) 1
(C) Change every time
(D) None
ANSWER :( A)
12. Data selector basically same as
(A) Decoder
(B) Multiplexer
(C) De-multiplexer
(D)Encoder
ANSWER: (B)
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
13. Carry generate in Carry Look Ahead adder is
(A) A + B
(B) A.B
(C) A’B’
(D) A’ + B’
ANSWER: (B)
14. Which of the following exhaust even parity?
(A) 10011000
(B) 11111111
(C) 10101010
(D) Both B & C
ANSWER: (D)
15. One to many “is called as
(A)Adder
(B) Multiplexer
(C)De Multiplexer
(D) Encoder
ANSWER: (C)
16. Which of the following circuit can be used as parallel to serial converter?
(A) Multiplexer
(B) De-Multiplexer
(C) Decoder
(D) Digital Counter
ANSWER: (A)
17. A 4-bit parallel adder can add
(A) Two 4 - bit binary numbers
(B) Two 2 -bit binary numbers
(C) four bits at a time
(D) 4 bits in sequence
ANSWER: (A)
18. Time delay in the addition process is called
(A) Sum propagation delay
(B) Borrow propagation delay
(C)Actual propagation delay
(D) Carry propagation delay
ANSWER: (D)
19. Encoder has _____ input lines and _______ output lines
(A)2ⁿ ,1
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
(B) 1, 2ⁿ
(C) 2ⁿ, n
(D) n, 2ⁿ
ANSWER: (D)
20. Combinational circuits depends on
(A)Present input
(B) Future input
(C) Past output
(D) Present & Past output
ANSWER: (A)
Part – B (Each Question Carries 4 Marks)
21. The following switching functions are to be implemented using a Decoder F1=∑m gm
(1,2,4,8,10,14) F2=∑m gm (2,5,9,11) F3=∑m gm (2,4,5,6,7) , then what is the minimum
Configuration of the decoder
(A) 2 to 4 line
(B) 3 to 8 line
(C) 4 to 16 line
(D) 5 to 32 line
ANSWER: (C)
22. The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than
the 2-bit input B. The number of combinations for which the output is logic 1, is
(A) 4
(B) 5
(C) 7
(D) 6
ANSWER: (D)
23. The Boolean function realized by the logic circuit shown is
(A) F = ∑m(0,1,3,5,9,10,14)
(B) F = ∑m(2,3,5,7,8,12,13)
(C) F = ∑m(1,2,4,5,11,14,15)
(D) F = ∑m(2,3,5,7,8,9,12)
ANSWER: (D)
24. Without any additional circuitry an 8:1 MUX can be used to obtain
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
(A) Some but not all Boolean functions of 3 variables
(B) All functions of 3 variables but none of 4 Variables
(C) All functions of 3 variables and some but not all of 4 variables
(D) All functions of 4 variables
ANSWER: (C)
25. The Boolean function f implemented in the figure using two input multiplexers is
(A) AB’C + ABC’
(B) ABC + AB’C’
(C) A’BC + A’B’C’
(D) A’B’C + A’BC’
ANSWER: (A)
26. How many 4:1 multiplexer are required to generate 128:1 multiplexer?
(A) 42
(B) 43
(C) 44
(D) 40
ANSWER: (B)
27. What is the minimum number of2:1MUX are required to implement two-input AND gate,
OR gate and EX-OR gate, respectively?
(A) 1, 2, 2
(B) 2, 1, 1
(C) 1, 1, 2
(D) 2, 2, 1
ANSWER: (C)
28. If only one multiplexer and one inverter are allowed to be used to implement any Boolean
function of 𝒏 variables, what is the minimum size of the multiplexer needed?
(A) 2nline to 1
(B) 2n-1 line to 1
(C) 2n-2 line to 1
(D) 2n+1 line to 1
ANSWER: (B)
29. How many outputs does a BCD decoder have?
(A) 4
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
(B) 8
(C) 10
(D) 16
ANSWER: (C)
30. The following multiple switching functions are to be implemented using a single decoder and
OR gates:
f1 = Σm (1, 2, 8, 10, 14)
f2 = Σm (2, 3, 5, 9, 15)
f3 = Σm (0, 2, 4, 5, 6, 7)
Which of the following is the minimum configuration of decoder needed?
(A) 2 to 4 line
(B) 3 to 8 line
(C) 4 to 16 lines
(D) 5 to 32 lines
ANSWER: (C)
Part C(Each question Carries 12 Marks)
31. Design a 2 bit magnitude comparator. The expression for the A greater than B
(A) A1B1’+A0B1’B0+A1A0B0’
(B) A1B1+A0B1B0+A1A0B0
(C) A1B1’+A0+A1A0
(D) A1B1’+B0+B0’
ANSWER: (A)
32. Consider the 4-to-1 multiplexer with two select lines S1 and S0 given below
(A) P’Q+QR’+PQ’R
(B) P’Q+P’QR’+PQR’+PQ’R
(C) P’QR+P’QR’+QR’+PQ’R
(D) PQR’
ANSWER: (A)
33. Consider the circuit shown below. The output of a 2:1Mux is given by the
function (ac+bc)
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
(A) F = X1’+X2
(B) F = X1’+X2+X1X2’
(C) F=X1X2+X1’X2’
(D) F = X1+X2’
ANSWER: (C)
34. If only one multiplexer and one inverter are allowed to be used to implement any
Boolean function of 𝒏𝒏 variables, what is the minimum size of the multiplexer needed?
(A) 2nline to 1
(B) 2n-1 line to 1
(C) 2n-2 line to 1
(D) 2n+1 line to 1
ANSWER: (B)
35. The following multiple switching functions are to be implemented using a single decoder
and OR gates:
f1 = Σm (1, 2, 8, 10, 14)
f2 = Σm (2, 3, 5, 9, 15)
f3 = Σm (0, 2, 4, 5, 6, 7)
Which of the following is the minimum configuration of decoder needed?
(A) 2 to 4 line
(B) 3 to 8 line
(C) 4 to 16 line
(D) 5 to 32 line
ANSWER: (C)
36. The 3 x 8 decoder shown has active low outputs. Which of the following options
represents the realization of 𝐹1and 𝐹2?
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, RAMAPURAM
FACULTY OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
(A) 𝐹1(𝐴,𝐵,𝐶,𝐷)=Σ𝑚(1,9,12,15), 𝐹2(𝐴,𝐵,𝐶,𝐷)=Σ𝑚(0,1,2,3,4,5,7,8,10,11,12,13,14,15)
(B) 𝐹1(𝐴,𝐵,𝐶,𝐷)=Π𝑀(1,9,12,15), 𝐹2(𝐴,𝐵,𝐶,𝐷)=Π𝑀(0,1,2,3,4,5,7,8,10,11,12,13,14,15)
(C) 𝐹1(𝐴,𝐵,𝐶,𝐷)=Π𝑀(1,9,12,15), 𝐹2(𝐴,𝐵,𝐶,𝐷)=Π𝑀(6,9)
(D) 𝐹1(𝐴,𝐵,𝐶,𝐷)=Σ𝑚(1,9,12,15), 𝐹2(𝐴,𝐵,𝐶,𝐷)=Σ𝑚(6,9)
ANSWER: (A)
